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FIFO
- 用verilog编写FIFO，并编写了相应的测试向量-Write FIFO Verilog
5-verilog-programs
- the file contains 5 verilog source codes 1. varying pulses 2. DRAM 3. FIFO 4. UART 5. 16 bit divider
FIFO
- Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
fifo
- 采用verilog语言的fifo设计。用notpad编辑-Verilog language fifo design. Edited using notpad
10_100m_ethernet-fifo
- 本源码源自于网络，采用verilog编写完成10M以太网到100M以太网的FIFO转化。-The source from the network, using verilog written 10M Ethernet 100M Ethernet FIFO conversion.
FIFO
- FIFO verilog VHDL-FIFO verilog VHDL
fifo
- 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
async-fifo
- Verilog codes for asynchrounous fifo design
FIFO
- 是用verilog HDL写的基于FIFO的串口发送机的设计，很详细的代码，很值得学习，已经验证通过-With verilog HDL based on FIFO serial transmitter design, write code, it is worth learning, has been verified by.
fifo-code
- Verilog代码：同步\异步FIFO。包含格雷码计数器.-Verilog code: syncronous\asyncourous FIFO. containing gray counter.
FIFO-and-CAM
- verilog code for gray counter,synchronous and asynchronous fifo
FIFO
- 用verilog做的FIFO程序，仿真通过-FIFO procedures to do with verilog simulation by
fifo
- 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
asynchronous-FIFO-verilog
- FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write add
fifo
- 这篇文档主要是描述了fifo的作用，里面有用verilog写的源码，及其综合后的结果-This document mainly describes the role of the FIFO inside useful verilog to write source code, and its consolidated results
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
fifo
- FPGA Verilog语言编写的fifo模块-The fifo module of FPGA Verilog language
verilog_fifo.tar
- Verilog FIFO model independent
synchronous-FIFO
- 同步fifo的使用verilog案例讲解-The use of synchronous fifo verilog case to explain
FIFO-[Compatibility-Mode]
- fifo specification for designing verilog