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Verilog
- 基于Verilog HDL的通信系统设计一书的源代码，大家可以下载，参考一下-Verilog HDL-based communication system design of the book source code, you can download, refer to
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
i2s_rel1_2
- I2S verilog HDL code including test environment
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
HDB3
- 用Verilog HDL语言进行HDB3编码，并通过Quartus Ⅱ仿真验证-With the Verilog HDL language HDB3 coding, and simulation by Quartus Ⅱ
ca_gen
- 此Verilog程序产生用于GPS卫星导航信号的C/A码，输入信号有时钟、时钟使能、复位、给定的卫星编号，输出产生的C/A码。此程序在代码上进行优化，占用了更少的资源。-This procedure generated Verilog for the GPS satellite navigation signals C/A code, the input signal with the clock, clock enable, reset, given the satellite number,
c21_pn_code_generator
- 精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
DAC8812
- DA转换，Verilog HDL 编的，可实现DA转化。DA芯片用的是DAC8812，实现16位数模转化。-DA conversion, Verilog HDL code, the DA conversion can be achieved. DA-chip using a DAC8812, 16-bit analog-to achieve transformation.
watch
- 基于verilog-HDL的电子秒表电路，采用quartusII72编译仿真，经下载测试通过。-Verilog-HDL-based electronic stopwatch circuit simulation using quartusII72 compiled by downloading the test.
source11-12
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
hdl
- 这是用Verilog HDL写的可调占空比分频控制器，可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
VerilogHDL
- 王金明：《Verilog HDL 程序设计教程》程序-Wang Jinming:
cpld11245
- 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率 测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频 模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等 主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设 计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要 求。-Introduced, such as the accuracy
VGA-VerilogHDL
- 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
c19_CICfilter
- 精通verilog HDL语言编程源码之5--CIC积分梳状滤波器设计-Proficient in verilog HDL source language programming of 5- CIC Integrator Comb Filter Design
c20_cordic_computer
- 精通verilog HDL语言编程源码之6--CORDIC数字计算机的设计-Proficient in language programming verilog HDL source of 6- CORDIC digital computer design
c23_RS_decoder
- 精通verilog HDL语言编程源码9——RS(204,188)译码器的设计-Proficient in verilog HDL source programming language 9- RS (204188) decoder design
seg7led
- Verilog HDL源码，显示器段数码管数字累加，测试通过-Verilog HDL source code, the display segment digital tube digital cumulative, testing through
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
16_FIR
- 16阶FIR滤波器--本设计用VERILOG HDL语言串行DA算法实现16阶有限频率响应滤波器！-16-order FIR filter- this design language VERILOG HDL serial DA algorithm limited frequency response of 16-order filter!