搜索资源列表
auk_sdsdi
- 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
FpgaDesignOfWirelessCommunicationsCodeExamples
- 无线通信fpga设计代码实例，包括MATLAB和Verilog HDL 语言实例，供大家学习和研究-Fpga design of wireless communications, code examples, including examples of MATLAB and Verilog HDL language, for them to learn and study
key
- Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. P
i2c_AT24C04_Verilog
- 用Verilog HDL语言编写的AT24C04程序，并用数码管显示，已经过测试，很好用-With the Verilog HDL language of the AT24C04 procedures and use digital tube display, has been tested, very good to use--
SDR
- FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.
viterbidecoder
- viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
MovingAverageFilter
- This zip file contains the moving average filter code written in verilog HDL
verilog
- 讲述的是verilog HDL 的一些实际应用与联系。还宝库奥一些总结性的知识。-About the verilog HDL and contact some of the practical application. Treasure-house of Austria is also a number of conclusive knowledge.
async_fifo
- verilog HDL写的异步fifo代码及测试平台，直接可用，可生成RTL代码-asynchronous fifo write verilog HDL code and test platform, directly available, can generate RTL code for
i2c
- verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
i2c.tar
- i2c core for verilog hdl
i2c_customer_pack
- i2c core for verilog hdl
yiweiDCTbianhuan
- 一维DCT变换的Verilog HDL源程序，在ISE中已经通过编译，可以参考里面的文档。-One-dimensional DCT transform Verilog HDL source code, in the ISE has been through the compilation, you can refer to inside the document.
Verilog-Hdl_Circuit_Design
- Verilog-Hdl Circuit Design 电路设计-Verilog-Hdl Circuit Design
Chapter1-5
- 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例
Chapter11-13
- 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个
VerilogHDL_tuxiang
- 介绍一种用于卫星姿态测量的CMOS图像敏感器--STAR250的时序驱动信号，并使用Verilog HDL语言设计驱动时序电路。经布线、仿真、测试后验证了驱动信号的正确性。 -Introduce a measurement for the satellite attitude CMOS image sensor- STAR250 timing drive signals, and use the Verilog HDL language design-driven sequential circ
hdl
- 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
asias_dds
- 一个简易的信号源，具有多种波形发生功能还有扫频，调制，频率计等相关功能-My project is on Direct Digital Synthesiser using Verilog HDL.This project is doing by me on july 2009 in summer training at NIT Kurukshetra, India. This DDS system generate the square wave, Triangular wave,Sine wa
Move071221133_32
- 用Verilog HDL语言或VHDL语言来编写，实现32位的桶形移位器。 并在Quartus Ⅱ上实现模拟仿真；-With the Verilog HDL language or VHDL language to write to achieve 32-bit barrel shifter. To achieve in the Quartus Ⅱ simulation