搜索资源列表
ldpc_decoder_802_3an
- 802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，
LDPC_Encoder_Verilog
- Verilog语言编写的LDPC编码程序
ldpc_encoder_802_3an.v
- LDPC 编码的Verilog源代码，我没有验证，不知道效果如何，与大家分享，供大家参考。
ldpc_vc
- ldpc编码的vc例程，编译通过，详细的解释了ldpc编码的原理-vc-encoded ldpc routine, the compiler through a detailed explanation of the principle of encoding ldpc
Framer
- ISE平台下的verilog的QC-LDPC编码，经仿真没有问题-ISE platform verilog QC-LDPC coding, no problems by simulation
ldpc_c_code
- LDPC码在基于BP (Belief Propagation) 的迭代译码相结合的条件下具有逼近Shannon 限的性能，是继turbo 码后在纠错编码领域又一重大进展。压缩文件中给出了LDPC在高斯信道下的c程序。-LDPC codes based on BP (Belief Propagation) Iterative Decoding of combining conditions with performance approaching Shannon limit on the heel
VLSI_Architectures_for_ECC
- This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to sever
the-decoding-algorithm-of-ldpc
- ldpc译码算法介绍及fpga verilog系统方案设计，包括log_bp算法、min_sum算法、scaling_min_sum算法等-introducing the ldpc code decoding algorithm and the related system design，including the log_bp,the min_sum and the scaling_min_sum
ldpc-encode
- 深空通信中AR4JA码编码的研究与实现，ＡＲ４ＪＡ码是ＬＤＰＣ码的一种，文件中是Ｖｅｒｉｌｏｇ语言的硬件实现。-Research and Implementation of the Deep Space Communications AR4JA coding, AR4JA code LDPC codes a hardware implementation of the Verilog language file.
LDPCtest
- ldpc编码器ru算法的verilog语言的完整实现，希望对您有用-ldpc encoder, RU, VERILOG，altera
dvb_s2_ldpc_decoder_latest.tar
- 用于数字电视机顶盒的DVB-S2的LDPC编码的解码模块，verilog代码-For digital TV set-top boxes of DVB- S2 LDPC coding, decoding module of verilog code
ldpc
- 移动通信技术中信道编码的LDPC码的Verilog hdl 实现-Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
MS_LDPC
- 移动通信技术中信道编码的LDPC码的译码Verilog hdl 实现-Decoding Verilog hdl channel coding of mobile communication technology to achieve LDPC codes
vnp
- 移动通信技术中信道编码的LDPC码的VNP的Verilog hdl 实现-Channel coding of mobile communication technology LDPC code VNP realization of Verilog hdl
QC-LDPC-decoder-FPGA
- 文章提出了一种可以兼容不同码率规则和非规则准循环低密度校验码(LDPC)的部分并行译码结构, 用Verilog语言开发，基于该部分并行结构在Altera公司的StratixII-EP2S90器件上验-This paper presents a part of different bit rates can be compatible with the rules and irregular quasi-cyclic low density parity check code (LDPC) de
ldpc576
- 基于wimax协议的低密度奇偶校验码LDPC的VERILOG实现，亲测可用。-WiMAX protocol based on the low density parity check code VERILOG LDPC implementation, pro test available.
e60a9bd4-ef5c-4c89-bfb3-9da40d5e4aba
- 低密度校验码 ，很好用的代码，功能已经实现编码和译码(Low density parity check code, very good code, the function has been achieved encoding and decoding)
src
- 用verilog实现ldpc最小和译码算法(This code is for the decode of MS-algorithm based on LDPC.)
ldpc_decoder_802_3an
- LDPC的编码模块和解码模块，实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)