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DDSFPGA_cylone
- dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
magnitude
- Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algori
GFEMultiplierTaps
- 用于生成GF(2^m)有限域中乘法器的Verilog HDL源文件的C程序
GFEConsMulTaps
- 用于生成GF(2^m)有限域中常数乘法器的Verilog HDL源文件的C程序
GFEInvertor
- 用于生成GF(2^m)有限域元素求逆器的Verilog HDL源文件的C程序
pn
- 用Verilog语言生成7位的小m序列，产生pn码
nptel-cad1-02
- Verilog notes - Part 2 from IIT M-Verilog notes- Part 2 from IIT M
nptel-cad1-04
- Verilog notes - Part 4 from IIT M-Verilog notes- Part 4 from IIT M
cml
- 基于Verilog的数字基带通信系统 3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course des
digital_frequency
- 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
VerilogPPT
- 我正在学习Verilog,发现了这个PPT教程，很好用。介绍给大家，希望能帮助那些和我一样刚开始入门的朋友。-I' m learning Verilog, found that PPT tutorial, easy to use. Introduced to everyone, hoping to help those who, like me, started to get into a friend.
Verilog_Quickstart
- James M. Lee 的大作，学verilog必备图书-verilog quick start
hm
- 汉明编码和解码的硬件描述语言（verilog），其被编解码的数据为M序列。 建议运行软件为Quartus.-failed to translate
fpga_dds_coylone_2
- dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
signal
- EP2C5Q208C8 verilog 产生m序列 50M晶振分频得到时钟，可以选择10种时钟- -！-EP2C5Q208C8 verilog 50M m-sequences generated by dividing the crystal clock, you can choose from 10 clock--!
MSequenceGenerator
- 5位的M序列发生器，verilog代码实现。5次本原多项式采用f(x)=x^5+x^2+1-5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
jf
- verilog编写的alu模块4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出-Verilog modules prepared by the ALU4bit ALU (arithmetic logic unit) design is given in the design of alu input and ou
m_serial
- x^8+x^4+x^3+x^2+1, 这个本原表达式，m序列，国赛中的一个题，用verilog编写，里面有详细讲解，经过我认真验证。-x^8+x^4+x^3+x^2+1 m serial
m_sequence
- 用verilog语言描述了M序列（伪随机通信）的编码、解码、纠错等功能，本人通过了Quartus II 以及Modelsim的仿真。-Verilog language descr iption of the M sequence (pseudo-random communication) encoding, decoding, error correction, I passed the Quartus II and Modelsim simulation.
mxulie
- m序列的verilog代码以及测试程序，希望对大家有用哦，花了时间写的-m sequence Verilog code, and test procedures in the hope of everyone Oh, it took time to write