搜索资源列表
m_seq_test_2
- 产生m序列的一个verilog程序，n=4.还有它在modelsim上的测试程序-a project generates m sequence and its test code
Design-exercise-M_sequence
- 通信系统电路设计练习： M序列编码/解码器的设计 作业的背景及训练目的 为了给通信专业的同学们提供一个设计实践的机会，在最短的时间段内掌握数字设计的动手能力，提高Verilog语言的使用能力，所以专门设计了这样一个难度适中的数字通信系统设计练习。本练习是根据工程实际问题提出的，但为了便于同学理解，对设计需求指标做了许多简化。希望同学们在设计范例和老师的指导下，一步一步地达到设计目标。期望同学们能在两至三周内，参考设计范例，独立完成自己的设计任务，在这一过程中学习用Verilog
ss
- verilog语言编写的基于M序列的编解码设计-verilog language design M-sequence-based codec
am29bdd160g
- 16 Megabit (1 M x 16-bit/512 K x 32-Bit), amd 公司 2.5 V电压, flash存储器仿真读写verilog 模型。-16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory verilog model.
M_code
- m序列实现,里面含verilog代码和教程，适合学习-m code
m_4_generater
- m序列发生器，verilog hdl语言 ，4位-m-sequence generator, verilog hdl language 4
m_seq
- Verilog HDL 实现的4位二进制 16个m序列产生-Verilog HDL m_seq
cmi
- 运用4阶m序列产生信号源 即消息码 用verilog编程实现cmi的产生-The use of fourth-order m-sequence generator source message code Verilog programming cmi generation
SDRAM50M
- 黑金开发板上基于芯片FPGAEP4CE15F17C8N中SDRAM，我自己编写的Verilog程序。时钟设定的是50M，希望可以帮到大家。-Black gold development board based on SDRAM chip FPGAEP4CE15F17C8N, my own writing Verilog program the clock setting is 50 m, the hope can help you
shuzixinhao
- 使用verilog编程，实现m序列发生，m转化为曼彻斯特编码。已经过仿真，拥有vt文件。-Use verilog programming, the realization of m sequence, m into Manchester coding. Simulation, has been with vt.
mPsequences
- m序列信号发生，用verilog编写，在fpga上可实现-m sequences
bluespec-h264_latest.tar
- H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
m_xulie
- 在quaritusII的开发环境下，verilog语言编写的m序列发生器代码，这种算法简短而有效，非常实用。-In quaritusII development environment, verilog language of m sequence generator code, this algorithm brief but effective, very practical.
RANGEN
- 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-seq
m_sequence_fpga
- 采用Verilog语言编写的伪随机序列——m序列，可用作通信系统输入数据源。-Use Verilog language- m sequence pseudo random sequence, and can be used as input data sources in communication system.
bin_count
- i m sending hdl code of dm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.-i m sending hdl code of ofdm using verilog and vhdl with all blocks contain fft,ifft,scrambler,transmitter,receiver.
DIVIDER
- M进制计数器 verilog code for divider-verilog code for divider verilog code for dividerverilog code for divider
blocking-and-nonblockng-MIT
- The difference of blocking and non blocking in verilog by M I T
DS_GMSK_MD
- 文件由两部分组成，直扩GMSK调制的matlab仿真程序和Verilog硬件程序。完成了对信号的扩频编码，GMSK调制，硬件程序中的高斯滤波器调用自matlab仿真产生。包括ds_gold_gmsk.m,mseq31.m,zhikuoGMSK.m以及d_encode.v,code_convert.v,frame.v,DS.v,gauss_filter.v,DS_GMSK_MD.v等编码，组帧，滤波，扩频，调制众多源码-Document consists of two parts, DSSS MS
ADC
- verilog At the last, before starting fist go through the FPGA NEXYS2 Board manual. It will be useful for you for this interfacing and also for the future. Best of luck…, try this one because practice makes man perfect. And, yes also if you have a