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cpu5.10_modelsim
- 用verilog编写的8位最简cpu代码，能实现简单的加减运算，存储运算，以及寄存器操作。-Verilog prepared with 8 simple CPU code, to achieve a simple addition and subtraction, memory operations, as well as register operations.
DDR2-controller
- My package named design DDR2 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory. It can be a separate chip or integrated into another
DDR3-SDRAM-controller
- My package named design DDR3 Synchronous Data Random Access Memory by verilog.The memory controller is a digital circuit which manages the flow of data going to and from the computer s main memory.
verilog_sdram
- I used code verilog. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to
ROM
- 使用Verilog语言编写的ROM，根据ROM逻辑，自己写的一个ROM，并仿真实现功能-read only memory
TCAM
- FPGA VERILOG TCAM (ternary content addressable memory)是一种三态内容寻址存储器，主要用于快速查找ACL、路由等表项。-FPGA VERILOG TCAM (ternary content addressable memory) is a ternary content addressable memory, mainly used to quickly find ACL, routing entries.
ram256x8
- 256*8存储器，采用Verilog语言编写-256*8 memory, using Verilog language
MEMCTRL
- 存储器控制器，采用verilog描述，FPGA实现-memory controler
VHDL100
- 本文件包含100个Verilog实例，有存储器，时钟，椭圆滤波器，状态机等。有助于初学者的学习。-This document contains 100 examples of Verilog, there are memory, clock, elliptic filter, state machines. Help beginners to learn.
NAND01GR3B_VH1
- 存储器verilog仿真代码，可以产生仿真向量对存储器测试。flash存储器选用march算法进行仿真测试。-Memory Verilog simulation code, you can generate simulation vector on the memory test. Flash memory selection of March algorithm simulation test.
codes
- my codes....................................................................................................
MemoryBIST
- memory的BIST代码，verilog-The memory BIST codes, verilog
MemControl
- Memory Controller verilog code.
ahb_slave
- 异步memory ahb lite slave接口verilog代码-verilog code of ahb lite slave for memory interface
pcie_ctrl_module
- pcie genx4 控制器模块 verilog，直接读取内存和写入内存-pcie gen4 controller module verilog, direct memory read and write memory
MEM
- hereby i have attached memory controller vip by using system verilog hope this will be helpfule for u
OV7670_DDR2_VGA
- 在FPGA下的视频采集显示，采用纯Verilog编写，其中包括有OV7670摄像头，高速存储器DDR2，ADV芯片的VGA。-In FPGA video capture display, using pure Verilog prepared, which includes OV7670 camera, high-speed memory DDR2, ADV chip VGA.
MemoryGame-master
- 在开发板EGO1上实现的图形记忆游戏，白块按下确认建，黑色块不按确认键-memory game in verilog
N25Q00AA13E_VG13
- This a source code for flash memory in verilog and the flash memory used is samsung k9 whose module can be found online-This is a source code for flash memory in verilog and the flash memory used is samsung k9 whose module can be found online
idwt
- Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 4 Verilog Units Built simulation executable G:/Techscope/On going Mtech/Miniproject/1DDWT/xilinx/top_dwt_isim_beh.exe Fuse Memory Usage: 101756 KB Fuse