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MIPS
- 用verilog语言描述的CPU各部分及相关链接-It about CPU s component and relationship which use verilog
MIPS-processor-Verilog-code
- 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instruct
cycle_code
- verilog实现了MIPS多周期（5周期）的CPU-verilog MIPS 5 cylce
MIPS-multi-cycle-(Quarters-II--Verillig)
- Multi cycle MIPS processor verilog
mips--cpu
- 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic de
Verilog-Source
- mips 处理器verilog文件， 适合做处理器开发的人员参考-the mips processor verilog file suitable processor development reference
s_mips
- FPGA verilog mips processor - pipeline reference
MIPS_shift_32bits
- MIPS架构下的32位桶形移位器的verilog源码-32-bit barrel shifter verilog MIPS architecture of the source
MIPS
- MIPs Processor in Verilog
mips.tar
- VERILOG CODE FOR 16- bit ripple carry adder
MIPS
- 用verilog编写的简单的类MIPS多周期流水化处理器实现，基本功能包括9条指令和两位动态分支预测，压缩包里的word详细说明了结构中的细节-Written by verilog simple class multi-cycle pipelined MIPS processor, the basic features include 9 instruction and two dynamic branch prediction, compressed bag word specifies th
mips
- Verilog语言开发的基于mips指令集的流水线cpu，只支持部分指令-Verilog language-based development pipeline cpu mips instruction set support only part of the instruction
mips
- 基于mips架构的五级流水线硬件实现。使用verilog-Based on the five-stage pipeline hardware architecture mips
OExp13-SOC
- 使用Verilog编程搭建的测试平台，并连接了VGA等外设，使用MIPS汇编编写逻辑完成的躲避球小游戏(Use Verilog programming to build the test platform, and connect the VGA and other peripherals, using MIPS assembly to write logic to complete the dodge ball game)
wuhao
- C语言编程以及MIPS汇编语言还有logisim的简单实现，算法(C language programming and MIPS assembly language, as well as a simple implementation of logisim, algorithm)
Chapter4
- MIPS is a reduced instruction set computer (RISC) instruction set architecture (ISA)[1]:A-1[2]:19 developed by MIPS Technologies (formerly MIPS Computer Systems). The early MIPS architectures were 32-bit, with 64-bit versions added later.
Chapter8
- The architecture greatly influenced later RISC architectures such as Alpha. As of April 2017, MIPS processors are used in embedded systems such as residential gateways and routers.
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
OpenMIPS
- 《自己动手做CPU》书后源码 包含各章节实例 分节使用(source code of mips CPU)
mips-cpu-master
- CPU设计，已通过模拟，有需要的自行下载吧(CPU design has been simulated)