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cf_fp_mul_p_5_10
- verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
cf_fp_mul_p_8_23
- verilog浮点乘发器，特定数据结构，指数底为10,利用pipeline-Verilog float by their hair, a specific data structure, the index for the end of October, using pipeline
pipe
- verilog编写的流水线模块-Verilog modules prepared by the Pipeline
pipelined-mips-cpu
- 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
firfilter14
- 用Quartus II实现综合布线，要求充分利用Altera Stratix/Stratix II的器件的DSPBLOCK资源，Quartus II综合出的系统最高工作频率达到270Mhz以上.用Verilog进行编程。-Pipeline FIR structure。
adder16_2
- 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
gcd_performence
- 基于流水线设计的性能优先的gcd算法的verilog 代码 频率可达500M-based pipeline design gcd for high clock
DataMemory
- datamemory code in verilog for pipeline processor
dp
- datapath code in verilog for pipeline processor
InstMemory
- instruction memory code in verilog for pipeline processor
4add
- verilog 实现两级流水线加法器 源代码 以及测试代码 adder16_2.v test_adder16_2.v-verilog Implement two pipeline adder source code and test code adder16_2.v test_adder16_2.v
32bit-RISC-CPU-IP
- 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction p
cordic
- 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
PipelineCPU2
- Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
My_RASrm
- 流水线处理器的Verilog代码，结构简单，基本功能-the pipeline processor，code in Verilog
Homework4
- 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
cordic
- verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
src
- 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
CHU92A
- MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
s_mips
- FPGA verilog mips processor - pipeline reference