搜索资源列表
wince+spi
- verilog vcspi file with testbench
UART
- 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
UARTtransmitter
- UART Transmitter. VHDL code and its testbench.
cascaded_adder
- implementation of cascade adder with verilog plus testbench
asynfifo
- 异步fifo，用Verilog编写，包含testbench，已经通过调试，需要的下载-Asynchronous fifo, to prepare to use Verilog, including testbench, debugging has been passed, the need to download
alu
- ALU modeling verilog codes and testbench
TestBench
- 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_log
Springer_2006_SystemVerilog_for_Verificatio_Chris
- A Guide to Learning the Testbench System Verilog Language Features
Lecture_Verification
- Writing testbench in verilog
Stepper_controller_MAx
- stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog qu
interleaver
- 交织编码器的verilog代码实现，此外有testbench和波形。-the verilog code for the interleave encoder, with the testbench code and waveform screen print.
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
testbench(vhdl)
- 是学习数字电路设计verilog语言，及Writing testbench的首先好书。-wrting testbench
FifoAndTestbench
- 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
fifo_tb
- verilog implementation of 16X4 fifo with testbench
verilog-testbench-preliminary
- 本文简单介绍了逻辑验证的入门知识—如何编写TESTBENCH进行逻辑测试-This paper briefly introduces the logic verification started- how to write TESTBENCH logic test
verilog-testbench-preliminary
- 硬件描述语言verilog的testbench的写作方法-the writing method of the testbench of verilog
Verilog testbench入门
- 本文档介绍了testbench的编写规范，通过实例讲解深入浅出学会testbench的编写
System-verilog-Overview
- Verilog overwied. it has writing verilog testbench guidlines
FIFO_RAM
- 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)