搜索资源列表
DCM_12M_1M
- xilinx下DCM输出12Mhz和1Mhz-Verilog DCM xilinx ISE
I2C
- I2C/IIC 总线接口驱动，在Altera和Xilinx的FPGA上跑过，Verilog编写，Craftor原创。V1.1。代码中还包含了24C02的读写测试程序，可直接用。-I2C/IIC Bus Driver, written in Verilog, v1.1. By Craftor
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
XilinxFPGA(1-60)
- 系统地讲述了Xilinx FPGA的开发知识，包括FPGA开发简介，Verilog HDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISEd开发环境使用指南等-Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL La
turbo_encoder
- 在赛灵思的FPGA上实现turbo码的编码程序,使用Verilog语言实现。-Implemented on Xilinx FPGA in the turbo coding principle, the use of Verilog language.
WirelesscommunicationFPGAdesign.Verilog
- 无线通信FPGA设计[田耘等编著][程序源代码]_2010112514154616，用Xilinx开发，调用modelsim进行仿真。-Wireless communication FPGA design [TianYun, etal] [source code] _2010112514154616, use Xilinx development, call modelsim simulation.
XAPP134_SDRAM_Verilog
- Xilinx XAPP134 SDRAM Verilog
FPGASDRAMverilog
- 一个基于Xilinx FPGA的DDRSDRAM的Verilog控制代码，使用的FPGA为Virtex完整源代码。-A Xilinx FPGA-based control DDRSDRAM the Verilog code for the Virtex FPGA using the full source code.
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
in-ModelSim-and-Xilinx-lib
- 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹，用来放xilinx的各个库文件，故可以起名 xilinx_lib。类似于Xinlinx的安装文件：\..\\Xilinx\verilog\src中的各个库文件，在xilinx_lib文件 下新建各个文件夹，命名规则为：若src中的文件夹名为unisims，则在xilinx_lib文件夹下新建 为unisims_ver的文件夹，与此雷同，新建名为simprims_ver、Xilinx
Xilinx
- verilog codes for designing decoders , adders
IVK_DVI_DVI_Pass_Through_Demo
- Xilinx IVK demoboard 上DVI to DVI 範例程式源碼-Xilinx IVK example programs on the DVI to DVI pass through demo code
Xilinx
- Demux modules and test simulations with various combinations of input and output vectors.I am new to Verilog.I am learning it through a electronic system design course on my college.I am interested in downloading a single .zip file from this site,Ver
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code
verilog-HDL-learning
- 从零开始学verilog HDL ，包括Altera实验板原理图，xilinx实验板原理图和一些实验源程序-From scratch learn verilog HDL, including Altera experimental board schematic, xilinx test board schematics and source code of some experiments
jtag-Verilog
- JTAG verilog code for xilinx fpga
counter
- 基于XILINX XC3S300的计数器程序，编程语言VERILOG-XILINX XC3S300 based counter program, programming language VERILOG
FPGACPLDXilinx-ISE-5.X--verilog
- FPGACPLD设计工具Xilinx ISE 5.X使用详解》配套光盘-FPGACPLDXilinx ISE 5.0--verilog
Verilog-HDL-Design
- FPGA入门的，云创工作室很好地一本书，主要以XILINX公司的芯片为主!-A very good book from Yunchuang studio for FPGA newer,and this book mainly talks about the verilog HDL and the XILINX FPGA!