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Verilog_Development_Board_Sources
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
multi8x8
- 该源码为8位乘法器的VHDL语言描述,由一个8位右移寄存器,2个4位加法器例化成8位加法器,一个16位数据锁存器构成。采用移位相加的方式,从被乘数的低位开始,与乘数的每个位移位相加求和。最后实现其乘法器功能。-The source code for the 8-bit multiplier in VHDL language to describe, from an 8-bit right shift register, two 4-bit adder example into 8-bit add
mul
- 八位乘法器的VHDL程序,按照乘法的运算规则利用分支语句判断所有情况,最后累加求的结果-8 multiplier VHDL programs, in accordance with rules of multiplication operations to determine all the circumstances of the use of a branch statement, the final cumulative result of demand
VHDL-based-8-bit-multiplier
- 基于VHDL的8位乘法器运算程序,运用移位迭代法运算得出-VHDL-based 8-bit multiplier operation procedures, the use of shift operations derived iterative method
8bit-Shift-and-Adder--multiplier
- 8位乘法器,经移位相加算法来实现的,用的VHDL语言-8-bit multiplier, adding the algorithm to realize the shift of
fVerrilog_Devr
- 朋友,我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的,现在就将她的Verilog源码也一并贡献给大家:8位优先编码器,乘法器,多路选择器,二进制转BBCD码,加法器,减法器,简简单易懂状态机,四位比较器,7段数码管,i2c总线,lcd液晶LCD显示出来,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL so
8bit-multiplier
- 8位二进制数乘法器VHDL实现8位二进制数乘法器设计,乘法通过逐项移位相加原理来实现,从被乘数的最低位开始,若为1,则乘数左移后与上一次的和相加;若为0,左移后以全0相加,直至被乘数的最高位。 -8-bit binary multiplier VHDL 8-bit binary multiplier design, multiplication by itemized shift sum principle, starting from the least significant bit of
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器,采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件,运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and