搜索资源列表
交通灯_XIN
- 使用vhdl语言编写的交通灯控制程序,带有完整的实验报告。-use of the VHDL language traffic lights control procedures, with a complete report of the experiment.
110detector_lab
- 一个简单的探测110三位的探测器,用逻辑图和vhdl描述,包括实验报告和测试图。-a simple survey of 110 three detectors, and a logical map vhdl descr iption, including reports and experimental test plan.
jhvhjhk
- 乒乓球游戏机实验报告实验人: 大火虎设计课题: 用VHDL设计一个乒乓球游戏机,用开关来摸拟球手及裁判,用LED来模拟乒乓球,采用每局十一球赛制,比分由七段显示器显示. 设计思路: 采用按功能分块,将整个电路分成若干子程序,利用不同的子程序来实现记分,显示,键盘控制。设计过程: 1) 对4MHZ信号进行分频,得到所需的1HZ,及七段显示器所需的频率.存为CLOCKMAKE.VHD(注:仿真时所加的信号频率比这要高。)。 2) 设计一个子程序来描述裁判,左击球手,右击球手的动作对LED显示的影响,
DigitalClock01
- 此硬件仿真程序选用VHDL编译,上传的是它的实验报告,其中包括全部源码和报告分析-this hardware simulation program VHDL compiler choose, it is uploaded to the experiment, including full source code and Reports Analysis
EDA实验3
- 基于vhdl语言的简单跑马灯程序 带完整报告。-vhdl language based on the simple Bomadeng procedures with a full report.
shixian.rar
- 该文件是一份本人设计的实验报告,报告内详细说明了用VHDL语言,设计一个三位动态显示的计数器。采用模块化得设计,设计通过了仿真以及下载实现。总的文件是:shixian.vhd,下面包括四个元件:jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd.,this paper uses vhdl to complement a design about how to make three leds display at the same time.
LCD.rar
- 有限状态机的设计——LCD显示控制实验,用VHDL编写程序,整片报告,Finite state machine design- LCD display control experiments, using VHDL programming, the whole report
EDAreport
- 用VHDL实现秒表功能,即使时间为60分钟,实验报告格式,代码在文档最后。仿真软件使用quartus2-Using VHDL stopwatch function, even if the time is 60 minutes, the test report form, the code at the end of the document. Simulation software use quartus2
lock
- EDA课程设计报告 - 电子密码锁设计实验 密码锁密码为4位-Curriculum design EDA Report- electronic locks locks password experimental design for four
shujujiegou
- 数自逻辑实验报告有关于83译码器的编写,用VHDL编写程序-Since the logic of the report of the number of experiments on the preparation of 83 decoder using VHDL programming
VHDL_digital_lock_design
- VHDL课程的源代码数字密码锁的设计与实现的实验报告,内附源代码-VHDL source code for the course digital code lock design and implementation of the experimental report, included the source code
ROM_based_sine_wave_generator_VHDL_design
- VHDL基于ROM的正弦波发生器的设计的实验报告,内附源代码-ROM-based sine wave generator VHDL design of experiment reports, included the source code
VHDL_design_of_sequence_detector
- VHDL中序列检测器的设计的实验报告,包括源代码-VHDL in the design of sequence detector test reports, including the source code
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
parallel-output-controller-(POC)
- 并行输出控制器,实现CPU与打印机之间的通信,程序基于VHDL语言,内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
pid
- 采样量化,实现数字PID功能,并观察了PID实现后的误差。包含测试文件和实验报告-Sample quantization, digital PID function, and after observing the realization of the error of PID. Contains the test documents and test reports
four
- 大学VHDL实验科目报告四位全加器设计报告-University of VHDL test subjects reported four full adder design report
VHDL-1-7
- VHDL课程的7个实验的实验报告附代码。-seven experiment reports of VHDL
VHDL乘法器的设计
- 基于VHDL语言的乘法器的详细设计实验报告。
数字基带信号的传输码型发生器设计实验报告
- vhdl语言,数字基带信号的传输码型发生器设计,附代码