搜索资源列表
hdlc
- HDLC协议的VHDL源码。接收和发送模块，以及所用FIFO的IP核（Xilinx公司）。-The code of HDLC protocol.Receive and transmit module is contained.
sram64kx8
- 基于VHDL的一种SRAM模块，简单，但是可参考性强-A VHDL-based SRAM modules, simple, but can be refered strongly
wave
- 可控脉冲发生器的VHDL源代码。设计文件加载到目标器件后，按下按键开关模块的S8按键，在输出观测模块通过示波器可能观测到一个频率约为1KHZ、占空比为50 的矩形波。按下S1键或者S2键，这个矩形波的频率会发生相应的增加或者减少。按下S3键或者S4键，这个矩形波的占空比会相应的增加或减少。-Controllable pulse generator of the VHDL source code. Design documents loaded to the target device and p
DCM
- Xilinx公司诸多型号开发版中的一个模块，能够实现1到16次倍频和分频等功能。使用时现在ISE集成开发环境下利用VHDL进行例化。本文档为个人学习总结-Xilinx, a number of models developed version of a module, be able to achieve 1-16 times multiplier and divider functions. ISE now use integrated development environment for
i2c
- 来自opencore网站的I2C总线模块，经过验证可以使用-Opencore site from the I2C bus module, you can use a proven
fpga-fpdpsk
- FSK/PSK调制顶层文件 ，正弦波模块 ，正弦波模块初始化文件 ，振幅调整及波形选择模块 ，频率显示值地址产生模块 ，频率步进键核心模块 ，弹跳消除电路-FSK/PSK modulation top-level documents, sine-wave modules, module initialization file sine wave, amplitude adjustment and waveform selection module, the freque
LFSR
- verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) mo
ETH
- 该系统通过顶层模块，调用4底层模块实现。4大模块底层模块为：cpu模块、发送模块、接收模块、mii模块-The system top-level module, called the bottom module 4. 4 large modules underlying module: cpu modules, transmit modules, receiver modules, mii module
VHDL-clock
- VHDL的程序设计模块，很有用那个，密码锁。-for vhdl！！
CPLD
- ad采集的小模块，实现串口转并口的功能，串口是SPI的接口-ad collector modoudle ad ad ad ad ad da da da da shuzi moni moni shuzi caiji caiji caiji caiji caiji caiji caiji
spi
- 三线spi接口，用verilog实现，作为一个模块，可以接收并行数据，然后串行发送-Three Line spi interface, using Verilog implementation, as a module, can receive parallel data, and then send the serial
FFT
- Verilog实现的FFT模块，供OFDM调制系统使用，可供大家参考学习-Verilog implementation FFT module for the OFDM modulation system used for your reference study
spitoi2s3
- spi转i2s的verilog程序，fpga是总模块，spi和i2s是子模块，shiftreg是转换-spi transfer i2s the verilog program, fpga is the total module, spi, and i2s is the sub-module, shiftreg is to convert
CPLD-CRACK-SIEMENS-200PLC
- 可用来破解分析西门子200 PLC与模块的通讯协议，基于ALTERA CPLD EPM240的设计. 需要配合分析板配套使用。-Analysis can be used to crack the Siemens 200 PLC and the communication protocol modules, based on the ALTERA CPLD EPM240 design. The need to tie in with the analysis supporting the
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
ref-sdr-sdram-verilog
- SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
alarm_system
- 电子闹钟：基于fpga的电子闹钟设计，采用模块化方式-Electronic alarm: FPGA-based electronic alarm clock design, modular approach
LCD_VHDL
- 液晶模块输出VHDL程序 程序实现的功能是标准的16×2字符型液晶模块上显示字符串-LCD module output VHDL procedures to achieve the function of the procedure is a standard 16 × 2 character LCD module to display the string
S9_PS2_LCD
- 键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
8237
- 关于vhdl对硬件接口8237的编程，可以在进行fpga/cpld设计是作为模块用到-VHDL for the hardware interface on the 8237 programming, you can carrying out fpga/cpld design is used as a module