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ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
alarm_buffer
- 是用VHDL写的一个常用的ALARM BUFFER,相信对电子设计的朋友有所帮助~
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
counter
- 这是用VHDL设计的十进制计数器，两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
vheader
- 将VHDL源文件中提取常量转换成C/C++的头文件。用于VHDL的固件和主机程序间的同步，如：寄存器地址，缓冲区长度，版本号等。-This short program converts the constants in VHDL files into C/C++ header files. It is useful to sync the VHDL firmware and C/C++ host program in, for example, register address, buffer
congxianchaoshengshujucaiji
- 在研究超声检测技术以及高频信号采集和处理技术发展趋势和PCI总线的特点基 础上，提出了一种基于PCI总线的超声数据采集卡的实现方案。在硬件方面，系统由模 数转换模块、数据缓冲模块、接口模块和逻辑控制模块等四个功能模块构成，着重研究 了接口芯片PCI9052的数据传输方式，采用原理图+VHDL的方法设计了板卡的内部控 制逻辑和数据缓冲模块，并进行了相关的时序仿真和逻辑验证。-Ultrasonic testing in research and high-frequency sign
auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
FPGA-DSP
- vhdl编写的FPGA与DSP接口程序，在FPGA内分配了两块双BUFFER与DSP进行通信-vhdl prepared FPGA and DSP interface program, the FPGA within the allocated 2 pairs of BUFFER to communicate with the DSP
Practica_3
- SP converter in vhdl and counter and buffer
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
Rom_Control_FPGA
- 用VHDL语言写的ROM控制器，对于编写BUFFER的同志可以用来参考。具有一定价值。-Written in VHDL language using ROM controller, for the preparation of the comrades BUFFER can be used for reference. Has a certain value.
FIFO24_CS8416[1]
- Fifo buffer vhdl code
FIFO24_psconv
- fifo buffer vhdl code
FIFO_ise11migration
- fifo buffer vhdl code
atapi_ctl_2_5
- fifo buffer vhdl code
atapi_ctl_2_6
- fifo buffer vhdl code
lab1(mka)
- RGB vga driver for manipulating the colours of a given image buffer. The code has beeen written in vhdl
VHDL-for-Datapath
- MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg
Buffer
- parametrizable register and mux in VHDL of data rage, using std_logic_vector type
rs485
- communication rs232 in vhdl with clock divider, counter, buffer, rs232tx, rs232rx.