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hsk4571_clock
- 数字时钟 VHDL实现，可调节时分秒，在QUATTUS||9.0下编写，可在9.0及以上版本运行并下载，芯片为Altera的Cyclone3 EP3C8T1-Digital clock VHDL realization, minutes and seconds can be adjusted in QUATTUS | | 9.0 under preparation, can be run in the 9.0 and above versions and download, chips for
debouncer_vhdl
- debouncer in vhdl with clock devider parameter and number of inputs
alarm
- 利用vhdl和verilog两种方式可以实现的fpga芯片的数字钟，其中包含多个可设计改动的个性化模块。源代码利用quartusii平台写作，可移植性很强。-Using vhdl and verilog fpga can be achieved in two ways-chip digital clock, which includes several design changes personality module. Source code using the platform quartu
multiclock
- 以VHDL为基础的多功能数字钟的实现功能程序，包括时钟，闹钟，计数等功能。-In VHDL-based implementation of multi-function digital clock procedures, including clock, alarm clock, counting and other functions.
CLK_DIV
- 时钟变化的VHDL语言，应用fpga仿真。-VHDL of clock
FPGA
- 数字钟，实验程序描述，vhdl语言描述，看电视剧广发卡三季度发卡了-Digital clock, experimental procedures described, vhdl language descr iption, watching TV wide hairpin hairpin three quarters of the
RAM_VHDL
- 用VHDL描述了一个32KBit的独立的读写时钟、使能、地址的双口RAM，-VHDL descr iption of a 32KBit with independent read and write clock, enable, address the dual-port RAM,
1123212
- 用VHDL写的一个数字时钟程序，调试成功-Use VHDL to write a digital clock procedures, debugging success
shuzhizhong
- 实现时钟显示,各个模块代码都有，对提高VHDL有帮助-Achieve clock display, each module has a code, help to improve the VHDL
alarm
- VHDL，多功能数字钟：具有年、月、日、时、分、秒计数显示功能，以24小时循环计数；具有整点报时功能；可以对年、月、日、时、分及秒进行单独校对，使其校正到标准时间-VHDL, multifunction digital clock: a year, month, day, hour, minute, seconds count display features a 24-hour cycle The whole point timekeeping function possible for
LCDtime
- 基于DE2板子上EP4CE115F29C7的用lcd1602显示时钟的VHDL语言，其显示的内容是时分秒，达到23:59:59后全部归零，重新计时。-Based on the DE2 board EP4CE115F29C7 use lcd1602 display clock VHDL language, its display when the content of the minutes, after reaching 23:59:59 all return to zero, the timi
minute_ct
- 采用VHDL语言设计的分钟计时器，是时钟设计的一部分，已仿真和测试通过。-Design using VHDL-minute timer, the clock part of the design, simulation and testing has been passed.
plx_r
- vhdl中的频率锁相环部分，完成时钟配置-part of the frequency locked loop vhdl complete clock configuration
eatfish
- vhdl语言，可以实现大鱼吃小鱼功能的时钟仿真仿真，经过测试可用-vhdl language, can achieve ones devour function clock simulation simulation, tested available
SHUZIZHONG
- VHDL语言编写的数字钟程序，在quartus软件下编写。-VHDL language digital clock program, prepared in quartus software.
shuzi-dianzi-zhong
- 基于VHDL的自动电子钟，并利用Quartus II 软件集成开发环境进行编译、综合、波形仿真成功-VHDL-based automatic electronic clock, and use the Quartus II software integrated development environment to compile, synthesize, waveform simulation success
Dll-Files
- clock divider code for vhdl
gcounter1
- 数字钟vhdl实现，在线测试无误，具有闹钟，对表功能-Digital clock vhdl implementation, online testing is correct, with alarm, the table function
8
- VHDL实验的程序，数字时钟，进行分秒计时，用数码管显示-VHDL experimental procedures, digital clock, for every minute timer with digital display
sy
- 利用VHDL语言设计的电子数字钟，有时、分钟、秒钟计数器、还有整点报时报警。-Design using VHDL language electronic digital clock, sometimes, minutes, seconds counter, as well as the whole point timekeeping alarm.