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dianzishizhong
- vhdl语言编写实现的数字电子钟程序代码-vhdl language code to achieve the electronic clock
matlab
- vhdl learning materials，-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
clockhms
- 自己写的数字钟源程序，VHDL语言，50M晶振，24小时计时制，可以清零，较时，闹钟。-I design a 24hr clock set, VHDL language, 50M crystals, it can be reset, relatively, the alarm clock
digtal_clock
- FPGA实现数字钟VHDL语言编写,包涵整点报时，清零，调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading
EDA
- 电子时钟 基于VHDL设计的建议电子时钟-DIGTAL CLOCK
clkNdiv
- 很经典的时钟分频代码，直接拿来可以使用 使用VHDL语言编写！-Very classic clock divider code can be directly used to use using VHDL language!
EDA_VHDL_shuzizhong
- EDA课程设计实验VHDL硬件描述语言实现数字时钟-EDA curriculum design experiments VHDL hardware descr iption language digital clock
shuzizhong
- vhdl数字钟通过fpeg仿真实现vhdl实验课设 -vhdl digital clock
Example23
- 设计一款多功能数字秒表的VHDL小程序，产生100Hz时钟的分频计数器-Design a multi-function digital stopwatch VHDL applet, generate 100Hz clock divider counter
Clockdivider
- VHDL CODE FOR CLOCK DIVIDER
CLK_TEST
- VHDL实现的8分频程序，经测试，在板上运行成功-8 divided clock
shuzizhong
- 数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
time-project
- 用VHDL语言实现数字时钟显示、控制、复位、加减、按键消抖-Using VHDL digital clock display, control, reset, subtraction, key debounce etc.
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter
DEMOs
- VHDL各类源文件，串并行转换，显示时钟，阵列显示等-VHDL source files of various types, serial to parallel conversion, clock display, an array of display
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
shizhong
- VHDL硬件语言实现时钟功能（只有分秒），在Quarter 2上的编程。-VHDL hardware language clock function (only minutes and seconds), the programming of the Quarter 2.
clockprj
- vhdl实现的万年历代码，年月日 星期 闹钟功能、-vhdl to calendar code, date week alarm clock function,
digitalclock
- 数字钟 初学VHDL时可参考 模10状态机 83译码器-Refer to die 10 when the state machine 83 decoder VHDL digital clock beginner
shuzipinlvji
- 1.用VHDL完成12位十进制数字频率计的设计及仿真。 2.频率测量范围：1Hz～10KHz，分成两个频段，即1～999Hz，1KHz～10KHz，用三位数码管显示测量频率，用LED显示表示单位，如亮绿灯表示Hz，亮红灯表示KHz。 3.具有自动校验和测量两种功能，即能用标准时钟校验、测量精度。 4.具有超量程报警功能，在超出目前量程档的测量范围时，发出灯光和音响信号。 -1 completed 12 with VHDL design and simulation of d