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三角波发生器，VHDL语言描述，通过信号分频等实现波形发生，已经在示波器上验证了，效果不过。-Triangular wave generator, VHDL language descr iption, such as through the realization of the signal waveform frequency has been verified on an oscilloscope, the effect, however.
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Clock Controller
There are often situations where one wishes to pass a predetermined number of clock pulses and then stop. The purpose of this problem is to design a controller in VHDL to gate a preset number of pulses form a free-running clock “CL
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DDS数字函数信号发生器，采用VHDL编写，可以产生正弦波、锯齿波、三角波信号，信号的频率和相位都可调。-DDS Digital Function Generator using VHDL write, you can produce sine, sawtooth, triangle wave signal, the signal s frequency and phase are adjustable.
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DDS信号源设计中关于正弦信号的波形发生器，采用VHDL编写完-DDS signal source design on the sinusoidal signal waveform generator, using VHDL prepared END
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FPGA单片机 vhdl编程正弦波信号发生器 加2个按键控制频率加减-FPGA Microcontroller vhdl programming sine wave signal generator plus two buttons control the frequency of addition and subtraction
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信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
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先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
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这是一个基于vhdl编写的正弦信号发生器，实现的功能为发生正弦波，给dac 0832采样-This is a sine signal generator based on VHDL code, realize the function of sine wave, give dac 0832 samples
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VHDL非常好的波形发生器资料 -VHDL very good waveform generator Information
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BPSK信号的载波调制，包含成型滤波器，上采用器以及载波生成器。(This file provides a transmitter based on BPSK signal, including shaping filter, upsampler and carrier generator.)
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VHDL代码，一些课本的小程序。包含3线-8线译码器，4选1选择器，6层电梯，8线-3线编码器，8线-3线优先编码器，8选1，BCD-7段显示译码器真值表，半加器，摩尔状态机，数字频率计，数字时钟，同步计数器，序列检测器的设计，序列信号发生器，一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
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采用FPGA（现场可编程门序列）编写VHDL语言设计多路同步脉冲发生器，对信号进行分频处理，实现四路信号相位相差T/16和T/8的延迟相位输出，实现的四路脉冲与传统的脉冲同步器不同，它具有高集成度，高通用性，容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide
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