搜索资源列表
aescore
- 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
xapp514_aes3-audio
- DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
khalil2006_true_random_number_generator
- a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are requ
AESsim
- AES alogrithm security encryption
freehdl-0.0.6.tar
- inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
63535312DCTofJPEG
- 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
aes128
- AES实现的效率如面积、吞吐量和功耗等，主要是由列混合变换和S 盒的实现决定的。S 盒单元的实现成为设 计的重点，它的硬件实现在很大程度上决定着整个芯片的面积大小。 -AES to achieve efficiency, such as area, throughput and power consumption, mainly by the S box column mixing transformation and the realization of decision. S box
fifo_template
- aes code with fifo control to memory
aes
- Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.
cunzip
- AES CODE FOR DECRYPTION
aes_core_latest-1.tar
- Simple AES (Rijndael) balance implementation and trade off size and performance-Simple AES (Rijndael) balance implementation and trade off size and performance
top_module
- AES Encryption Algorithm.... This Module gives the basic overview to indicate the flow of AES Algorithim at different stages by associating various Packages to the module-AES Encryption Algorithm.... This Module gives the basic overview to
aes_decrypt
- This the Top Module for AES Decryption algorithm-This is the Top Module for AES Decryption algorithm
test_dec1
- This Module creates the test Bench for AES Decryption Algorithm
sbox
- verilog code for s-box generation for AES algorith
decryption
- AES decryption in VHDL!! Wit LCD controls
09912007AEScoremodules
- aes descr iption architecture processes vhdl code with pipelining and throughput reduction with an aim to create a faster AES decoding system in FPGA
aes_core.tar
- 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
avs_aes_latest.tar
- AES algorithm decryption Encryption
AES-sopc--ip
- 在FPGA上实现了AES，并写了基于AVALON总线的接口，主要使用是VHdL实现，并在SOPC系统上定制了IP核。-FPGA to realize the AES, and write the AVALON based on the bus interface, the main use is VHdL implementation, and the SOPC system in custom made IP core.