搜索资源列表
web_cpu88.zip
- Intel微处理器8088的VHDL实现,可以用ModelSim进行仿真测试。,Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
lift.rar
- (1)用VHDL实现四层电梯运行控制器。 (2)电梯运行锁用一按钮代替(开锁上电),低电平可以运行,高电平不能运行。 (3)每层电梯入口处设有上行、下行请求按钮,电梯内设有乘客到达层次的停站要求开关,高电平有效。 (4)有电梯所处楼层指示灯和电梯上行、下行状态指示灯。 (5)电梯到达某一层时,该层指示灯亮,并一直保持到电梯到达另一层为止。电梯上行或下行时,相应状态指示灯亮。 (6)电梯接收到停站请求后,每层运行2秒,到达停站层,停留2秒后门自动打开,开门指示灯亮,开门6秒后电梯自动关门
ALU.zip
- VHDL实现cpu核心逻辑与运算单元模块的实现,完成4bit*4bit输入8bit输出的运算,可做加减乘除逻辑移位6种操作,the implementation of Arithmetic and logic unit based on VHDL, can do as the adder,subtractor,multiplier,divider,shifter and logic operation.
74LS160.rar
- 一个很实用的74系列的VHDL源码实例,可以很容易的学会VHDL语言,A series of 74 practical examples of VHDL source code, you can easily learn to VHDL language
dds(heli).rar
- DDS用verilog 实现,可以实现方波、正弦和三角,DDS using verilog realized, can be square wave, sinusoidal and triangular
实现PS/2接口与RS-232接口的数据传输
- 实现PS/2接口与RS-232接口的数据传输, 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。,The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received ch
trunk-hdlc.rar
- 高级链路层协议的实现,vhdl,fpga,- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码,在ModelSim中仿真通过,并且在ISE中能综合!即可以下载到FPGA中运行指令,指令可以根据需要定义,也可和相应的编译器配合使用,这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
TLC2543.rar
- 模数转换TLC2543十二位串行芯片驱动程序,经用已得证实.用都只需根据需要修改即可.,Analog-digital conversion chip TLC2543 12 serial driver, was confirmed by the use has. Using both can be modified only as needed.
EEPROM_RD_WR.rar
- 本程序包含:EEPROM的功能模型(eeprom.v)、读/写EEPROM的verilog HDL 行为模块(eeprom_wr.v)、信号产生模块(signal.v)和顶层模块(top.v) ,这样可以有一个完整的EEPROM的控制模块和测试文件,本文件通过测试。,This procedure includes: EEPROM of the functional model (eeprom.v), read/write EEPROM acts of verilog HDL modules (e
source_code.rar
- 一些源程序,主要包括CAN总线驱动、sdram VHDL实现、ucos2的移植、SDIO驱动、tcpip的实现、usb控制器代码、基于FPGA的雷达目标模拟器等,Some source code, including CAN bus driver, sdram VHDL implementation, ucos2 transplant, SDIO drivers, tcpip of implementation, usb controller code, based on the FPGA, s
mp3decoder.rar
- mp3 解码的verilog代码,通过仿真综合及验证,能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。,mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed docu
par_serial-and-serial_par-VHDL
- 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码,经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
ADC0832_test.rar
- ADC0832是一个8-bit的ADC转化芯片,工作频率为250Khz,最大频率可达400Khz,转化通道有两个,输入电压可分有单端或差分形式。本测试使用单端电压输入形式,从昔年的CH0输入电压,使用Xilinx XC3S200AN开发板,并且使用Xilinx ise工具中的ChipScope工具来查看转化后的DO数据是否正确。经验证,输入电压范围是0V--5.5V,当电压达到5.5V时,满刻度.,ADC0832 is an 8-bit conversion of the ADC chip, t
DIPC1.zip
- 5/3小波变换的vhdl代码实现,可以供参考,,5/3 wavelet transform vhdl code, you can for information,
ltc1196.rar
- TLC1196串行AD控制模块,可以实现对电压的信号采集,并以串行的方式传送到FPGA中,TLC1196 Serial AD control module can be achieved on the voltage of the signal acquisition, and serial transmission of the FPGA
cf_dpsk.rar
- 用VHDl语言写的一个DPSK的调制和解调程序,该程序可以实现相对相位调制解调。可以运行在xilinx ISE 或者是QuartusII下。 ,VHDl written in a language with DPSK modulation and demodulation process, the program can be achieved relative phase modulation and demodulation. Can be run on xilinx ISE or Qua
VHDL语言实现的arm内核
- 5个ram核,arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核,verilog写的,有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心,结构良好,简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目,国防科技大学牛人ShengYu Shen写的,原来放在opencores上,
ddc.rar
- 数字下变频器的matlab实现,一定的设计指标,可以用来知道vhdl程序设计,Digital Down Converter for matlab realized, certain design specifications that can be used to know VHDL Programming
oc_i2c_master.rar
- I2C core,经过验证可以在SOPC上运行的IP核,I2C core, verified SOPC can run on IP nuclear