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VHDL CPU部件
- 包括一个简单的ALU和一些寄存器、ROM的设计。有一些以TXT文件格式存在，用的时候只要改一下格式即可。
CPU_16.rar
- vhdl语言的16b cpu代码 全部的代码我会依次上传 另有说明txt文本,VHDL language 16b cpu code all the code I will upload the text otherwise stated txt
MICO8_DEMO_03_18_08.ZIP
- Lattice 超精简8位软核CPU--Mico8，开放所有源代码，包括VHDL，编译器，支持GCC编译器。可在Lattice所有FPGA和MachXO 器件上使用。本例包含示例和说明文档。对使用Lattice器件的用户或者学习CPU设计的人员有较高参考价值。,Lattice super-streamlined eight soft-core CPU- Mico8, open up all the source code, including VHDL, the compiler to supp
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
RiscCpu
- Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted
mcpu_1.06b
- MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD - one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable educational tool. The source
ALU
- vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
OR1200_verilog
- or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog descr iption of the risc cpu realize, cpu source code analysis and chip design source book
cpu
- 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
CPU
- 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
freerisc8_11
- 一个基于VHDL 的简单8位CPU的IP core核心代码-VHDL based on a simple 8-bit CPU core code of the IP core
cpu
- 简单CPU 能处理10条简单CPU指令 不包括IO指令-Simple CPU can process 10 a simple CPU instructions do not include IO commands
CPU_16_Beta_1.0
- VHDL CPU 16 16位的简易CPU 开发工具为Xilinx-VHDL CPU 16 a simple CPU in VHDL
cpu
- 基于十二条简单汇编指令构成的一个cpu 采用vhdl语言编写 内附源代码 工具sylinx-Based on 12 simple assembly instructions consisting of a cpu using vhdl language source code tool sylinx included
CPU
- 利用VHDL语言 开发设计一个小型CPU -Development and design using VHDL, a small CPU
CPU
- 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
cpu
- 16位的CPU的VHDL程序~~还有附加的生成波形，可以应用于课程设计中-16-bit CPU, VHDL ~ ~ There are additional procedures for generating waveforms, can be applied to curriculum design
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
cpu
- 设计一个简化的处理器（字长8位），并使其与内存MEM连接，协调工作。用VHDL以RTL风格描述。该处理器当前执行的指令存放在指令寄存器IR中。处理器的指令仅算逻指令和访问内存指令）。-Design a simplified processor (8-bit word length), and connect it with the memory MEM, and coordination. Described with VHDL in RTL style. The processor is c
cpu
- Simulating the work of cpu.(Simulating the work theory of cpu. By VHDL in ISE.)