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vhdl语言，实现数字钟的设计，用component实现-vhdl languages, digital clock design, component achievement
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这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development
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Digital Clock in Assembly
我的一个大学满分VHDL作品，数字石英钟的模拟程序。-Digital Clock in the Assembly a perfect score University VHDL works , the number of quartz crystal clock the simulation program.
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这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,
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朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code q
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数字电子钟设计，整点报时，时分秒分模块设计，另附实验报告和实验结果，内容详细不容错过,The design of digital electronic clock, the whole point of time when minutes and seconds sub-module design, an additional test reports and laboratory test results, the details not to be missed
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VHDL语言编写的一个六十进制计数器（用于分钟），一个脉冲输入引脚，一个复位引脚，8个BCD码输出引脚，一个进位输出引脚。与我的其它8个模块配套构成一个数字钟。-A 60 binary counter(for minute) programmed with VHDL language.A pulse input, a reset input, eight BCD code output BCD code, a carry bit output. It is one of my total 9 m
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用VHDL语言编写数字钟的程序，实现数字钟的几个功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
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用VHDL语言编写数字钟的程序，实现数字钟的完整功能，如计时、校时、闹钟和整点报时-Digital clock using VHDL language programs, digital clock several functions, such as timing, timing, alarm and hourly chime
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使用VHDL语言编程，烧录在芯片运行的倒数5秒响4声短铃最后一声长音的数字钟,The use of VHDL language programming, burn in the chip to run the last 5 seconds short bell ring 4 final say sound a long tone of digital clock
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dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
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数字时钟的实验，让读者了解数字时钟的原理，用vhdl实现它的方法，并学习vhdl的使用技巧-Digital clock experiments, so that readers understand the principles of digital clock using vhdl way to achieve it, and learn skills to use vhdl
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EDA设计实验，用VHDL编写的数字时钟代码，能显示分，秒，小时。根据所设置的频率不同，能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
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VHDL语言源程序，使用元件例化的方法设计简易数字钟-VHDL language source code, the use of components instantiated designed simple digital clock
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应用MaxplusII平台的数字时钟的VHDL源程序，可以解压后直接运行，已经过测试，希望对大家有所帮助。-Applied Digital Clock MaxplusII platform of VHDL source code can be run directly after decompression, has been tested, I hope all of you to help.
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VHDL的数字电子钟程序，供初学者参考哦！-VHDL digital electronic clock procedures, for beginners reference Oh!
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用VHDL语言写的实时时钟 用数码管显示 基于的控制芯片是EP1C6Q24C08-VHDL language used to write the real-time clock with digital display are based on the control chip EP1C6Q24C08
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大学VHDL实验数字钟源码，有的专业数字电路实验设计也有要求做的。-University of VHDL experimental digital clock source, and some professional digital circuit design has also requested to do so.
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该文件是用VHDL变成实现的数字钟程序，请指教！-The document is a VHDL implementation of the digital clock into the procedure, please advise!
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时、分、秒、实现数字钟的基本VHDL源代码。-Digital clock basic VHDL source code.
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