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数字系统设计报告，多功能电子钟，显示年月日星期时分秒，及校时等功能-Digital system design report, multi-functional electronic bell, show date when the minutes and seconds a week, and school functions when
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VHDL的数字时钟程序
24小时计数显示；
具有校时功能（时，分） ；
实现闹钟功能（定时，闹响）；-VHDL digital clock counting procedures showed that 24 hours with a school function (hours, minutes) the realization of an alarm clock function (timing, downtown ring)
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基于VHDL语言，用Top_Down的思想进行设计的数字钟。-Based on the VHDL language, using design thinking Top_Down the digital clock.
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这是一个用VHDL语言编写的数字电路程序，仅供学习参考。-This is a language with VHDL digital circuit procedures, only to learn the reference.
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使用VHDL开发的简易数字时钟软件，可以作为初学者熟悉定时器应用的实例程序。-Use VHDL to develop a simple digital clock software can be used as timers for beginners familiar with examples of the application process.
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基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
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DEMO2 数码管扫描显示电路/DEMO4 计数时钟
DEMO5 键盘扫描设计/DEMO6 波形发生器/DEMO7 用DAC实现电压信号检测/DEMO8 ADC电压测量/DEMO9 液晶驱动电路设计-DEMO2 digital tube display circuit scan/DEMO4 count clock scan design DEMO5 keyboard/DEMO6 Waveform Generator/DEMO7 implementation by DAC voltage si
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数字钟的VHDL源程序，可以实现校时，校分等功能，并在试验箱上运行成功-The VHDL source code digital clock, you can achieve at school, school grade features, and success in the chamber is running on
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关于数字钟的实现，用VHDL实现时，分，秒，的显示，并能报时-Digital clock on the realization of VHDL to achieve with hour, minute, seconds display, and time
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一个秒表的硬件设计，学习数字电路中基本RS触发器、单稳态触发器、时钟发生器及计数、译码显示等单元电路的综合应用。-The hardware design of a stopwatch, learn basic digital circuit in the RS flip-flops, monostable multivibrator, the clock generator and counting, decoding display unit integrated circuit applic
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以前学EDA的时候做过的四个小程序，分别是24/12小时制数字钟、数字频率计、乐曲播放电路、多人智力竞赛抢答器-EDA previously done when the four small procedures are 24/12 hour digital clock, digital frequency meter, circuit music players and many more devices quiz Answer
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用VHDL实现的完整数字钟代码，时分秒计时、校时、整点仿电台报时。-Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio.
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简单的数字时钟EDA设计，并通过电路的仿真和硬件验证，进一步了解计数器的特征和功能。-Simple digital clock EDA design, and through circuit simulation and hardware verification, and further understanding of the characteristics and functions of counters.
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VHDL数字闹钟实现，运用八位LED显示-VHDL realization of the digital alarm clock, the use of eight LED display
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数字时钟信号用vhdl语言描述的源代码他光放利用到各个电路中-Vhdl digital clock signal with the source code language to describe his use of light to release all circuits
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使用VHDL编写的数字PLL，对于想在FPGAzhong灵活使用时钟 的人有帮助。-Prepared by the use of VHDL digital PLL, the FPGAzhong would like flexibility in the use of the clock to help the people.
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基于VHDL的数字时钟的设计，能直接在开发板上看到运行结果-VHDL-based design of the digital clock can be seen directly in the development of on-board results
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基于CPLD的VHDL语言数字钟（含秒表）设计
利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。
-CPLD based on the VHDL language di
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基于VHDL语言的数字钟设计，附有完整的程序代码，并有仿真结果。-VHDL-based digital clock design, with a complete code, and have the simulation results.
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数字钟：显示，设置时间，设置闹铃（报时），秒表。
平台：quartusII 5.1。
说明：此版本中已将系统时钟调快，自己稍微改动一下即可，小小的考验，做出来会更有成就感！-digital clock：display time, set time, set alarm(use speaker to alarm), stopwatch.
platform: quartusII 5.1
comment: there s a place to change if you want th
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