当前位置：
首页 资源下载
搜索资源 - vhdl digital clock
搜索资源列表
-
2下载：
南京理工大学EDA实验多功能数字钟+闹钟+dds+am调幅。-Nanjing University of EDA test multifunction digital clock+ alarm+ dds+ am AM.
-
-
0下载：
基于quartus II 软件用vhdl语言写的数字时钟实验 源代码、最终生成文件全程奉献-Quartus II software-based language used to write the vhdl source code digital clock experiment, the resulting file full dedication
-
-
0下载：
实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作-Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously
-
-
0下载：
EDA用maxplus2开发设计的简易数字钟，适合初学者，vhdL语言-EDA maxplus2 in development and design of simple digital clock, is suitable for beginners, vhdL language
-
-
0下载：
用vhdl 实现数字时钟功能，基于fpga实现-Digital clock using vhdl function, based on fpga implementation
-
-
0下载：
上传的文件包括E有关EDA实验的程序，比如FIFO，秒表，数字钟，七段数码管，状态机检测序列-The files uploaded contain some source code of EDA experiments based on VHDL, such as FIFO, digital clock, stop watch, digital tubes and sequential detector.
-
-
0下载：
基于FPGA的实现一个电子时钟的VHDL语言-digital clock design with VHDL
-
-
0下载：
通过使用VHDL语言编写程序实现了数字钟的功能-Through the use of VHDL language procedures for the realization of the digital clock function
-
-
0下载：
VHDL语言编写的数字时钟程序，包括硬件设计的芯片管脚分配和功能代码等。功能包括时间的设定和显示。-VHDL language digital clock procedures, including hardware design, the chip-pin assignment and functional code. Features include time setting and display.
-
-
0下载：
Vhdl code for a working digital clock which can be displayed on a vga screen. The clock can be set using a single pushbutton. This project was written for nexys 2 board but can be easily ported to any other fpga using vhdl.
-
-
0下载：
VHDL编程数字钟，能够实现时间校正，闹钟，整点报时，显示日期，倒计时等功能。-The VHDL programming digital clock, time correction, alarm, hourly chime, such as date, countdown function.
-
-
0下载：
数字钟设计 计时计数器用24进制计时电路；
可手动校时，能分别进行时、分的校正；
整点报时；
选做：可设置闹时功能，当计时计到预定时间时，扬声器发出闹铃信号，闹铃时间为4s，并可提前终止闹铃。-Digital clock design
-
-
0下载：
vhdl数字钟，有校时校分整点报时的基本功能-vhdl digital clock school, the school divided the whole point timekeeping function
-
-
0下载：
digital clock vhdl language
-
-
0下载：
使用VHDL实现数字时钟，已在FPGA上验证-use VHDL to build a digital clock, has been validated on FPGA
-
-
0下载：
用quartusII编写的vhdl代码，在板子上输出的显示就是数字钟，也可以重置、设置时间。-With written in VHDL quartusII code, the output is the digital clock is displayed on the board, you can also reset, and the time.
-
-
0下载：
基于VHDL的数字时钟设计，能很好的模拟数字时钟显示-VHDL-based digital clock design, can be a good analog and digital clock display
-
-
0下载：
vhdl数字钟通过fpeg仿真实现vhdl实验课设
-vhdl digital clock
-
-
0下载：
用VHDL语言实现数字时钟显示、控制、复位、加减、按键消抖-Using VHDL digital clock display, control, reset, subtraction, key debounce etc.
-
-
0下载：
数字钟 初学VHDL时可参考 模10状态机 83译码器-Refer to die 10 when the state machine 83 decoder VHDL digital clock beginner
-
