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sycclk
- it s modul of clock in fpga vhdl where the cycle is 25 MHz enjoy
i2cBUS
- Altera的I2C总线FPGA程序,内有详细使用说明- The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source