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AssignmentP6
- 1. For the VHDL model given below (Code List One), compare the FIFOs implementations on CPLD and FPGA. (1) Synthesize and verify (simulate) the VHDL design of the FIFOs (2) For CPLD implementation (fit) of the FIFOs, how many MCs (macrocells)
watchvhd
- WATCHVHD硬件描述语言(VHDL)是一个顶级的一个停表类型项目。-WATCHVHD is a top level VHDL type project of a Stop Watch.
123123
- VHDL课程设计，交通灯的项目文件，已仿真通过。-VHDL course design, the traffic lights project file, already simulation through the.
FPGA
- FPGA交通灯说明： 1. 本程序使用VHDL加原理图方式设计而成。 2. 实验时，使用Quartus II软件完成了工程管理与下载验证，使用max+plus II软件进行了功能仿真。 3. 由于实验当时对原理图文件缺乏足够的认识，导致原原理图以及仿真输出文件已经丢失。现在的工程 RTL视图以及仿真输出波形均是在Quartus II软件下得到的。-FPGA traffic lights shows:1procedures for the use of the VHDL sch
project35
- Final project for an ALU vhdl implementation
Package
- Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 11
8b10b_encdec
- There are four VHDL modules in the 8b10b_encdec project:: • 8b10b_enc.vhd • 8b10b_dec.vhd • enc_8b10b_TB.vhd • encdec_8b10b_TB.vhd-There are four VHDL modules in the 8b10b_encdec project:: • 8b10b_enc.vhd •
traffic-light
- 用vhdl编写的交通灯程序，开发平台为quartusII。调试好的工程文件，可直接下载到实验箱-Written with vhdl traffic light program, the development platform for quartusII. Good debugging project files can be downloaded directly to the experimental box
pinlvji
- 用VHDL语言编写的频率计，在FPGA上使用，已验证，全工程文件-In the frequency of the VHDL language, on the FPGA has been verified, the whole project file
clock
- vhdl语言实现的时钟功能的quartus工程。在FPGA上运行可以得到时钟效果，并有调节功能。-vhdl language to achieve clock quartus project. Can get the clock running on the FPGA results, and regulatory function.
div16_dff
- 该项目用D触发器设计了一个基于VHDL的16分频的分频器，其中包括仿真时序图。-Of the project design with D flip-flop frequency divider 16 points based on VHDL, including simulation timing diagram.
logic_simulation_problem
- VHDL Logic simulation Project content.
ps2files
- Project descr iption for a VHDL mouse ps2 interface for the spartan 3 e board. do not take this into consideration because it s null i just only want to activate my account
lab555
- 利用FPGA，VHDL建立工程项目，实现dicegame功能-FPGA, VHDL Establishment of Project to achieve dicegame function
lab0-part1
- 利用FPGA，VHDL建立工程项目，入门项目，实现点亮LED-Use of the FPGA, VHDL projects, entry project, lit LED
tthrreefliifth
- 三层电梯控制器VHDL源程序源码码，是本人的毕业设计 -The three-tier elevator controller VHDL source code source code, is my graduation project
8051_latest
- this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code-this project is regarding 8051 microcontroller development in VHDL language using xilinx tool for synthesis of code
00.SW_LED_Nexys3
- 内容是关于FPGA的VHDL和verilog的程序，都是基于硬件项目的小程序-Program on the FPGA VHDL and Verilog, are based on a hardware project procedures
01.BTN_LED_Nexys3
- 内容是关于FPGA的verilog和VHDL的程序，都是基于硬件项目的小程序-Program on the FPGA VHDL and Verilog, are based on a hardware project procedures
20120720
- 北京大学信息科学技术学院开设的2012暑期课课程—基于FPGA上的VHDL设计，内容包含全部必选实验的工程文件和仿真波形。-Opened the 2012 Summer Course in Science, Peking University Institute of Technology- based on the FPGA VHDL design, the project file that contains all mandatory experiments and simulation