搜索资源列表
ManchesterCode
- VHDL编写的曼彻斯特编码程序，已验证通过，文件为完整的工程-VHDL, Manchester coding process has been verified through the file for the complete project
lab2parte1
- We want to show the values set through the switches SW8-1 on the 7-segment display and HEX0 Hex1. Values are denoted SW4 and SW8-5-one, shown in Hex1 and diplays HEX0, respectively. Your circuit must be able to show the digits 0
FPGA_Verilog-
- 关于VHDL程序设计的书籍，经典免费，书中主要描述 Verilog 语音的介绍以及项目例程-About VHDL programming classic books, free of charge, the book describes the Verilog voice introduction and project routines
clock____!
- The project is designed with the hour hand and the minute and the second time in the ISE software language. Vhdl written.
vga_-easy
- This project is designed to VGA Vhdl language.
FIR_poroje
- this project is about FIR FIlter By VHdl codes in the ISE.
DDS
- 基于DDS原理，利用VHDL语言进行正弦波、三角波、锯齿波、矩形波等波形的发生。包括完整代码和QUARTUS II工程。-Based on DDS principle, the use of VHDL, sine, triangle, sawtooth, square wave waveform occurs. Including the complete code and QUARTUS II project.
NAND_flash_verilog_vhdl
- 很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。- NAND Flash Controller Reference Design =============================================================================== File List 1.
Cyclone4_115_TV
- 基于Altera cyclone4_115芯片下的完整VGA端口开发工程，包括VHDL源文件，和项目工程文件，对于FPGA下的VGA端口开发很有参考价值。-Based on Altera cyclone4_115 chip under full VGA port development projects, including the VHDL source files, and project files, the VGA port for FPGA development of great r
VHDL_Starter_Examples
- 河北大学-VHDL实验课程相关的所有VHDL源代码，含具体的工程文件和原始课件，直接可以在Quartus II打开进行仿真-Hebei University-VHDL experiments related to the course all VHDL source code, including the specific project files and original software, you can directly open the Quartus II simulation
CPU_project
- CPU设计与实践实验源码，工程文件 ise。VHDL代码 可直接运行-cpu project
IIR_Biquad
- that is iir filter design in vhdl and it provides good method in that project designing.
VHDL_IUST_Fall2012_90611046
- carry ripple adder and 7segment with vhdl.i hopr people who use this project di not just cheat it
lcd
- 该压缩包内涵一个由VHDL语言编写的程序，里面是一个完整的项目工程，实现的功能是LCD12864液晶屏的显示-The connotation of a compressed package from the VHDL language program, which is a complete project, the function is LCD12864 LCD display
pacman_vhdl_xilinx
- VHDL version of Pacman. Intended to run under Spartan II over the Xess dev.board but easily portable to any other Xilinx platform. Contains full project with all bitmaps and sounds.
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
DDSforsinandcos
- 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
myfir
- VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
finaldesign_watch
- 基于VHDL的数字跑表源码，芯片采用ALTERA公司的ACEX1K 系列的EP1K10TC100-3，项目设计过程中，用EDA技术作开发手段，运用VHDL语言，实现从0.01秒到59分59秒59 的设计。-VHDL-based digital stopwatch source, ALTERA chip company ACEX1K series EP1K10TC100-3, the project design process, by means of EDA technology for th
counter_
- VHDL源代码+工程，可改变时钟的计数器-VHDL source code+ project, can change the clock counter