搜索资源列表
lock
- 基于VHDL的智能密码锁程序，能用EMP1270T144C5单片机下载，能够输入4—6位十进制密码，有重置密码、报警、点阵显示、数码管显示功能。quartus II 9.0编译成功。压缩包里有word文件的源码，打不开工程可以看看。代码较多但语句都很简单，有比较详细的注释。-VHDL-based smart lock program, can download EMP1270T144C5 microcontroller can enter 4-6 decimal code, there are
audioVHDL
- FPGA_Audio - project to implement and demonstrate audio on FPGA Using VHDL
JJ213_program
- 卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。-Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
ti_C6474evm_fpga_top
- Project file for VHDL design
DDSN
- quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
AVA6SV2_DIPLED
- A project in vhdl that uses 74hc595 to read up to 16 key and write to 4*7seg simultaneously in pure vhdl code.
wu4g
- Wake up network layer for a Hardware based radio project, written in VHDL.
CPU
- 计算机组织与结构课程设计，使用VHDL设计一个简单功能的CPU。该CPU拥有基本的指令集，并且能够使用指令集运行简单的程序。另外，CPU的控制器部分（CU）采用微程序设计方式。-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to g
ASK_DEMODULATION_AND_TEST_CODE
- ASK解调VHDL程序及仿真,项目已使用，好用-ASK demodulation VHDL procedures and simulation, the project has been used, easy to use
Runlength-Data-Compression
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is
digital-down-converter-ddc
- 这是用VHDL语言写的数字下变频模块，包含整个工程文件，数字下变频是软件无线电中的关键技术，可以直接用Quartus II打开。-this is a module of DDC(Digital Down Converter) with VHDL, it includes the whole project,you can open it with Quartus II directly.
blutooth
- A VHDL bluetooth transceiver UART project with python scr ipts.
zed_hdmi_720p
- zedboard板所用的HDMI工程文件，VHDL语言，适用于720P图像采集和显示-HDMI project file zedboard plate used, VHDL language, suitable for image acquisition and display 720P
tst_bench
- A test bench project in VHDL code
UART_CESHI
- 基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中-Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project
spi_verilog_master_slave_latest.tar
- 该项目从需要具有强大而简单的以VHDL编写的SPI接口核心开始，用于通用的FPGA到设备接口。 所产生的内核产生小而高效的电路，从非常慢的SPI时钟到超过50MHz的SPI时钟。-This project started the need to have robust yet simple SPI interface cores written in VHDL to use in generic FPGA-to-device interfacing. The resulting co
noc
- this the final project report on VHDL development on noc-this is the final project report on VHDL development on noc
F19UHQBIHWIQ1GR
- smart fan project for vhdl 5 part
FEJQR03IHWIQ3I9
- smart fan project for vhdl 5 part(2)