搜索资源列表
ise_c8051
- r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the
simu01
- spartan 3 series ADC vhdl code testbench
SPI-Core_nguyen
- SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE
1.2Register-VHDL-and-testbench
- 用d type flip flop 改成的n bit 的寄存器，分别用到了同步和异步2种方式-With d type flip flop into the n bit registers were used in the synchronous and asynchronous 2 ways
seq_detector
- 3比特的任意二值序列检测器(例如101、110、001等)。从任意序列中检测出三比特的序列。包含VHDL源码以及testbench测试源码程序。-The 3-bit binary sequence of any detector (e.g., 101,110,001, etc.). A three-bit sequence is detected from an arbitrary sequence. Includes VHDL source code and testbench test so
all-pole_filters_latest.tar
- All polar vector and its vhdl code with testbench
06168353
- The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compressio
Multiplier
- 我是2014级复旦的研究生。这是用VHDL语言设计的任意的M乘以N位的乘法器。设计中，被除数和乘数的位数是通过参数来设置的，可由你来修改。我已写好了testbench。可放心使用。-I am a 2014 graduate of Fudan University. This is an arbitrary M VHDL language designed by N-bit multiplier. Design, the dividend and the median multiplier is
TEXIO
- TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
testbench_top_level.vhd
- testbench for top level, vhdl, audio synthesizer, top level
CAVLE-h264
- 本压缩文件包含了h.264压缩算法中的CAVLE的编解码模块（Verilog和VHDL两个版本），包含有仿真的testbench测试文件，综合后可以直接使用-The compressed file contains the h.264 compression algorithm CAVLE codec module (Verilog and VHDL both versions), including a simulation testbench test file, can be used d
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
串并转换
- vhdl实现串并转换，其中附有源程序和testbench程序，可以用modelsim仿真
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
trafficlight
- VHDL实现红绿灯，multisim测试通过，可直接烧录到FPGA板上进行测试,带testbench-VHDL realize traffic lights, multisim tested, can be burned directly to the FPGA board for testing, with testbench
SPI-master-P-tb
- SPI master VHDL realisation Also contains TestBench
M_UartRecv0_tb
- rs232串口基于VHDL的testbench代码 很有用的 经过验正的 -RS232 serial port based on testbench s VHDL code is very useful to the RS232 serial port based on testbench VHDL code is very useful to pass the test
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench