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890714MODELSIM-SE-V5.5D
- Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed
ShirazHusainVSRD
- REVIEW:LOW POWER VLSI DESIGN TECHNIQUES EXPLORING SLEEP TRANSISTOR, FORCED STACK AND SLEEPY STACK
1
- DNA Cryptography and Trellis Algorithm
VLSI Architecture for Real-Time HD1080p
- 3d-hevc虚拟视点合成算法；硬件实现.VSRS算法(3d-hevc virtual view synthesis algorithm; hardware implementation;.VSRS algorithm)
ASIC Design Flow Tutorial
- Integrated Circuits are made from silicon wafer, with each wafer holding hundreds of die
bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi
Microwind
- A good images made by microwind for VLSI
Atalanta-M-2.0
- AUTOMATIC TEST PATTERN GENERATION TOOLBOX FOR VLSI TESTING AND FAULT COVERAGE MEASUREMENT
智能优化算法
- 优化技术是一种以数学为基础，用于求解各种工程问题优化解的应用技术。作为一个重要的科学分支，它一直受到人们的广泛重视，并在诸多工程领域得到迅速推广和应用，如系统控制、人工智能、模式识别、生产调度、VLSI技术和计算机工程等。鉴于实际工程问题的复杂性、约束性、非线性、多极小、建模困难等特点，寻求一种适合于大规模并行且具有智能特征的算法已成为有关学科的一个主要研究目标和引人注目的研究方向。 20世纪80年代以来，一些新颖的优化算法，如人工神经网络、混沌、遗传算法、进化。(Optimization te
Coding Files
- Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
VLSI_IEEE_2016_List
- VHDL IEEE 2016,2017 Project List
ALUYEDEK
- alu circuit design for vlsi and 4 bits alu
1999 masera TD
- required for vlsi communication engineers
4_542268753883168868
- Solutions for CMOS VLSI Design 4th Edition.
IDE
- thesis related to vlsi area, pll and frequency synthesizer div()
verilog workshop
- Verilog/SystemVerilog for Design and Synthesis is a comprehensive workshop covering the complete Verilog Hardware Descr iption Language and the synthesizable portions of SystemVerilog, including user-defined types, enumerated types, structures, and s
3. Comparator
- EXCLUSIVE OR and EXCLUSIVE NOR gates may be viewed as 1-bit comparators. Figure 1(a) shows an interpretation of the 74x86 XOR gate as a 1-bit comparator
3-spice
- SPICE (Simulation Program with Integrated Circuit Emphasis) is a general-purpose, open source analog electronic circuit simulator.
Chopper_IA
- A small-area low-ripple chopper instrumentation amplifier (IA) using a sample-and-hold circuit
CMOS Nested-Chopper
- A CMOS nested-chopper instrumentation amplifier is presented with a typical offset of 100 nV.