搜索资源列表
Full-Adder
- 用VHDL实现的全加器,采用dataflow style编写,是学习VHDL入门级的好范例. 包括主程序和测试程序-Full adder by using VHDL, dataflow style writing. It is a good example of VHDL especially for the entry-level leaner(Testbench included)
testbench_learn
- 自己写的一个移位寄存器的实例,该例子主要用来讲述verilog中的testbench的写作,以及在testbench中怎样使用task,以使仿真更加的高效简洁-Write your own instance of a shift register, which is mainly used to describe examples of verilog testbench writing, as well as how to use the testbench in the task, to m
QAM_verilog
- 基于FPGA的16QAM,用verilog编写,其中DDS为自己编写,含设计文件和testbench。已通过moldesim软件仿真。 -FPGA-based 16QAM, with verilog writing, including DDS for their preparation, including design files and testbench. Simulation software has been through moldesim.
System-verilog-Overview
- Verilog overwied. it has writing verilog testbench guidlines
fpga
- 有关FPGA的好多资料的综合汇总,包括夏宇闻-Verilog经典教程,Verilog-testbench的写法,Altera+FPGA/CPLD设计高级篇,Altera+FPGA/CPLD设计基础篇等好几本书,超值-A comprehensive summary of a lot of information about FPGA, including Xia Wen-Verilog classic tutorial, Verilog-testbench writing, senior Alte