搜索资源列表
51corevhdl
- 51单片机内核vhdl实现 xilinx平台的 -51 microcontroller core VHDL achieve Xilinx Platform
based-on-Xilinx-PCIe-Core-DMA
- 1， 支持由板卡发起的DMA操作，既可以将板卡内的数据快速传输到PC，也可以将PC的数据读取到板卡内。DMA的可以通过PCIe的BAR0空间控制。 2， 利用Xilinx LogiCORE Endpoint Block Plus硬核，兼容Virtex 5、Virtex 6、Spartan 6系列。无缝支持PCIe x8、x4、x1速率 。 3， 在板卡的终端是标准的FIFO接口，可以接入各种形式的数据，例如AD采样数据，光纤数据，DA数据。 4， DriverStudio生成的
Xilinx-Interrupt-Core
- 中断控制器，Xilinx公司应用于EDK中-Interrupt Core, Xilinx applied to EDK
fft_compare
- matlab file to compare the results of fft function of matlab with fft of xilinx core generator
lab5
- 用Xilinx内核生成器系统生成DCM内核 和存储器内核（ROM、RAM)等-DCM core and memory cores generated by Xilinx CORE Generator System (ROM, RAM), etc.
dds_key-feature
- dds key feature in this file i explain key feature of dds xilinx core.
xilinx-xadc-core
- Xilinx XADC driver for Linux v2.13.6.
nysa_sata_latest.tar
- The Xilinx CORE Generator™ is used to create a single-lane PCIe Endpoint Plus design. The generated PCIe system contains the PCIe endpoint plus block, GTP tiles, block RAMs, and clock and reset modules. The tutorial below shows how to create the
LCD-IP-CORE
- LCD Controller IP for Xilinx FPGA
XPS_Custom_IP_Tutorial_2
- Custom IP Core Development tutorial in Xilinx XPS
XPS_Custom_IP_Tutorial_3
- Custom IP Core Development tutorial in Xilinx XPS Part 3
XPS_Custom_IP_Tutorial_1
- Custom IP Core Development tutorial in Xilinx XPS Part 1
XPS_Custom_IP_Tutorial_4
- Custom IP Core Development tutorial in Xilinx XPS Part 4
XilinxFree.lic
- 这是许可在Xilinx Vivado 2015利用免费的IP核生成(This is the license to utilize free IP core generation in Xilinx Vivado 2015)
基于SOC的手持式频谱仪的软件设计与实现_邓嘉
- 一篇比较好介绍以zynq为核心设计嵌入linux系统的文献(A good introduction to zynq as the core design embedded Linux system documentation)
MAKEAMIF
- 用于生成xilinx开发环境中存储器ip core的mif数据文件的程序代码。(this program is used to generate mif file used by xilinx memory ip core.)
MAKEXCOE
- 用于生成xilinx开发环境中存储器ip core的coe数据文件的程序代码。(this program is used to generate coe file used by xilinx memory ip core.)
XILINX_DDR3_IP核使用教程
- 详细介绍了Xilinx DDR3 IP核的使用方法和注意事项(The usage and attention of Xilinx DDR3 IP core are introduced in detai)
can_v3_2
- XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)
xapp794
- 里面分为八个实验，一步一步教你使用system genertor for dsp 生成能供vivado使用的IP核文件。(It is divided into eight experiments, which teach you to use system genertor for DSP step by step to generate IP core files that can be used for vivado.)