SPI Master Core HDL: VHDL 93 Compatibility: all FPGAs, CPLDs parameterization: - variable data width - Phase/polarity configurable - selectable buffer depth - serial clock devision due to system clock package usage: IEEE

xilinx ML40X开发板 的CPLD 例程-the cpld demo of xilinx ml40x

Pseudo Random Binary Sequence (PRBS) generator for Xilinx XC9572XL CPLD.