搜索资源列表
xapp460
- xilinx hdmi tx rx verilog code
xapp856
- 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
XILINX
- Verilog汇编很牛叉 O(∩_∩)O哈哈哈~-Verilog
ddr_verilog_xilinx
- xilinx的ddr sdram控制器文档-xilinx of ddr sdram controller documentation
ddr2
- 基于Xilinx fpga的ddr2 控制器设计方法-Xilinx fpga-based controller design method of ddr2
Multiplier
- It s a design of a 4*4 multiplier based on Verilog, using Xilinx ISE.
sdram_vhd_134
- This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
c_xapp260
- xilinx应用指南xapp260的中文翻译版本。利用 Xilinx FPGA 和存储器接口生成器简化存储器接口。本白皮书讨论各种存储器接口控制器设计所面临的挑战和 Xilinx 的解决方案，同时也说明如何使用 Xilinx软件工具和经过硬件验证的参考设计来为您自己的应用（从低成本的 DDR SDRAM 应用到像 667 Mb/sDDR2 SDRAM 这样的更高性能接口）设计完整的存储器接口解决方案。-The use of Xilinx FPGA and Memory Interface Gen
c_xapp454
- 这是xilinx应用指南xapp454的中文版本。本应用指南说明与 Micron DDR2 SDRAM 器件连接时，Spartan™ -3 器件中 DDR2 SDRAM 存储器接口的实现。本文档先简单介绍了 DDR2 SDRAM 器件的特性，然后对 DDR2 SDRAM 存储器接口的实现进行了详细说明。-This is the xilinx application note xapp454 the Chinese version. This application note and t
sanfenpin
- verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in
CFO_Correction
- 载波频率同步Verilog程序 基于xilinx ise 实现-Carrier frequency synchronization Verilog program is based on xilinx ise to achieve
Processor_alu
- this Code is in verilog HDL. This Code is for piplined processor with 4 opcode. this will work in three cycle latch, decode and exicute.. test bench for xilinx ise is laos given
SDRAMController
- xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
A8255V4
- A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.
verilog_rs232
- 用verilog实现串行口UART控制器，适用于XILINX器件-verilog UART controller
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
uart1
- RS232(UART)串口传输，通过了FPGA验证功能正确-UART RS232 verilog HDL FPGA xilinx
ml505_mig_design
- Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1-Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1
I2C_code
- 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
topic
- DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA