搜索资源列表
VHDL
- VHDL对各种电路的基本实现，包括乘法器，触发器，加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
Multiple
- 高效的乘法器设计，既节约面积，又提高性能，同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
multiprocessor
- 简单的乘法器的内核测试，已经验证通过，VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
multi
- 8位乘法器，Quters编译环境VHDL代码-pluter VHDL Quters
Lab4
- 实现原码一位乘法器，但必须位数相同才行。-hdbadbkwdk
16bit_mult
- 16位的无符号数乘法器，自己写的，经得起验证，注释很详细-16-bit unsigned multiplier, its own written
maths
- multiplux,8*8的单片机乘法器-for the microcontroller
8bit_mult
- 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
multiplier8x8
- 8位定点乘法器，支持有符号数/无符号数运算。采用4-2压缩树结构，并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
mul8b
- 有VerilogHDL编写的8位乘法器，可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
4_bit_mul
- 四位乘法器,可以实现两个四位二进制数的乘法。-4_bit_mul
BBooth
- 基verilog 布斯乘法器 4位位宽，本人不才，仅做参考-Booth multiplier based verilog
jiaotongdengsheji
- 乘法器 简单的乘法器编译 用VHDL自己编的-Compiled using a simple multiplier multiplier VHDL own series
6345252
- FPGA应用实例，FPGA片上硬件乘法器的使用，编程语言vhdl-Application FPGA, FPGA-chip hardware multiplier to use, programming language vhdl
multiplier_ip
- 基于IP核的乘法器设计，multiplier_ip中包含完整的工程设计文件，用户可以在Xilinx ISE下运行-Based on IP core of design, multiplier_ip on time-multiplier contain complete engineering documents, users can run Xilinx ISE
mltiply_machine
- verilog语言写的乘法器，每一步经过验证，毫发无损，拿出来与大家共享，在quartus II 上编程，仿真在cyclone 2上！！谢谢！-written multiplier verilog language, every step of the proven, intact, and show to share the quartus II on programming, simulation in cyclone 2 on! ! Thank you!
pipe_mul8
- verilog实现的流水线8位乘法器，效率高，代码简洁经典-verilog implementation of pipelined 8-bit multiplier, efficient, simple and classic code
Multipliers
- 各种乘法器，不同算法类型的，适用于不同情况。(Various multipliers, different algorithmic types, are applied to different situations.)