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- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号。本系统用状态机来实现序列（1110010）的序列检测器的设计，若系统检测到串行序列 1110010 则输出为 1 ,否则输出为 0 ，并对其进行波形和功能仿真。-Sequence detection can be used to detect one or more groups formed by the binary code pulse train signal. The system implemented by the st
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- 序列检测器。用于检测一组由二进制码组成的脉冲序列信号，在数字通信中有着广泛的应用。当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出A，否则输出B。由于这种检测的关键在于正确码得收到必须是连续的，这就要求检测器必须记住前一次的正确码以及正确序列，直到在连续的监测中所收到的每一位码都与预置的对应码相同。在监测过程中，任何一位不相等都将回到某一状态（并不一定是初始状态）。-Sequential detector
Serial_ck
- 特定序列检测器，VHDL语言实现，采用状态机的编程思想，同时程序中的被检测序列可以稍微修改以满足自己的需要-Specific sequence detection, VHDL language, the use of state machine programming ideas, and the program sequence can be detected in the slightly modified to meet their own needs
detect
- 基于QuartusII的序列检测器，可下载到实验箱-Based on the sequence QuartusII detector, can be downloaded to test me
ztj
- 摩尔状态机检验程序，序列检测器，1100101检测-Moore state machine testing procedures, the sequence detector, 1100101 test
seqbet
- 10011序列检测器，verilog语言编写的检测器-10011 sequence detector
xulie
- 基于FPGA的任意序列检测器，其中有序列发生器-FPGA-based detection of any sequence, including sequence generator
Program2
- 将8位待测预置数作为外部输入信号，即可以随时改变序列检测器中的比较数据。写出此程序的符号化单进程有限状态机。-The 8-bit pre-measured as the number of external input signal, which can change at any time in the sequence comparison of the data detector. Write the symbol of this process a single process fini
seqdet
- 用VERILOG 语言进行的序列检测器设计，初学者多用于练习。-Sequence detector design
VHDL_design
- 以VHDL设计一有限状态机构成的序列检测器。序列检测器是用来检测一组或多组序列信号的电路，要求当检测器连续收到一组串行码（如1110010）后，输出为1，否则输出为0。-With VHDL Design into a finite state machine sequence detector. Sequence detector is used to detect the signal sequence of one or more groups of circuits, require th
zhuangtaiji
- 用状态机实现序列检测器的设计，并对其进行仿真和硬件测试。-With the sequence detector state machine design, and its simulation and hardware testing.
VHDL-node
- VHDL的一些实验代码，其中有4位可逆计数器，4位可逆二进制代码－格雷码转换器设计、序列检测器的设计、基于ROM的正弦波发生器的设计、数字密码锁的设计与实现-Some experiments of VHDL code, which has four reversible counters, four reversible binary code- Gray code converter design, sequence detection Design, ROM-based sine wav
machine-design-
- 状态机实现序列检测器的设计，了解一般状态机的设计与应用-State machine to implement sequence detector design, understand the general state machine design and application
vhdl
- VHDL实验 序列检测器的设计与实现-Design and Implementation of VHDL experimental sequence detector
State_Machine
- 状态机的VHDL实现，在quartus-ii7.2上测试通过，文件包括米利状态机，摩尔状态机，ADC0809的状态机实现，序列检测器和定时去毛刺的状态机实现。-State machine code in VHDL,successfully tested in quartus-ii7.2,the file contains mealy state machine,moore state machine,ADC 0809 and sequence detector achieved in state
Lab17_seq_detect
- 一个序列检测器，在时钟的每个下降沿检查数据。当检测到输入序列 din 中出现 1101 或 0110时，输出 flag 为 1，否则输出为 0。 （1）当cs = 1，wr 信号由低变高（上升沿）时，din 上的数据将写入由 addr 所指定的存储单元 （2）当cs = 1，rd = 0时，由 addr 所指定的存储单元的内容将从 dout 的数据线上输出。 -A sequence detector, check the data in each clock falling edge. Wh
schk
- 用状态机实现序列检测器的设计，熟悉用状态机设计各种序列检测器的思路和方法-Sequence detector state machine design, familiar with the ideas and methods of the various sequence detector state machine design
state
- verilog 应用状态机设计的序列检测器-verilog ，state machine
Sequence-detector
- VHDL环境下编写的序列检测器，当检测到设定序列时，硬件的提示灯会亮，也会发出警示音。-Sequence detector written in VHDL environment, when detected, set the sequence, the light will also alert tone hardware tips.
Sequential-detection
- 序列检测器的vhdl设计（用状态机实现序列检测器的设计，了解一般状态机的设计与应用。）-Sequential detection