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schk
- 熟悉用状态机设计各种序列检测器的思路和方用状态机实现序列检测器的设计-Familiar with the various sequence detector state machine design thinking and to use the state machine to achieve the design of the sequence detector
s101
- 用VHDL语言,设计一个“101”序列检测器,双过程描述编写-VHDL language, to design a dual procedure describes the preparation of "101" sequence detector.
m_seq
- 产生长度为15的M序列,将m序列产生的数据作为输入,送入一个序列检测器,该序列检测器在检测到连续的“1010”时,送出一个时钟周期宽度的指示信号-15 m_sequence ,and can test"1010"
10101-sequence-detector
- 课程设计之10101序列检测器的Verilog 实现-10101 sequence detector
The-state-machine-sequence-detector
- 状态机实现序列检测器。设计一个一个左移移位寄存器,用硬件设备上的两个拔码开关,预置一个8位二进制数作为待检测码,随着时钟逐步输入序列检测器,8个脉冲后检测器输出结果。-The state machine sequence detector. Design a left shift register, two on the hardware DIP switch and preset an 8-bit binary number as to be detected code, as the clo
xu-lie-jiance-qi
- 序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号,当序列检测器连续收到一组串行二进制码后,如果这组码与检测器中预先设置的码相同,则输出1,否则输出0。由于这种检测的关键在于正确码的收到必须是连续的,这就要求检测器必须记住前一次的正确码及正确序列,直到在连续的检测中所收到的每一位码都与预置数的对应码相同。在检测过程中,任何一位不相等都将回到初始状态重新开始检测。 状态机的工作方式就是根据控制信号按照预先设定的状态进行顺序运行。本实验就是要求当检测器收到一组二进制码后,如果这组码与检
Sequence-detector
- 序列检测器,检测(1110010)比较基础的检测器,可在此基础上进一步练习并改进.-Sequence detector, (1110010) The basis of comparison of the detector, on this basis, further practice and improve.
sequence-detector
- 序列检测器的设计与实现。功能要求:检测器有一个输入端X,被检测的信号为二进制序列串行输入,检测器有一个输出端Z,当二进制序列连续有四个1时,输出为1,其余情况均输出为0。如:X:1101111110110,Z:0000001110000。 -Design and Implementation of the sequence detector. Functional requirements: the detector has an input terminal X and the dete
work
- 这里面包含了从易到难的6个很经典的verilog例子,有序列检测器,3位乘法器,数字报表等-It contains from easy to difficult six very classic verilog example, a sequence detector, three multiplier, digital statements, and so on
xulie
- 序列检测器 用于BASYS2板子 教学用-this is a xulie checker
aa
- 这个程序就是序列检测器的vhdl实现,真麻烦啊-This program is the sequence detector vhdl achieve real trouble
detector
- 序列检测器,实验题第一题,懂的人都懂得,可以实现对1101的检测,使用状态机-Sequence detector
sequence
- 利用Basys2 FPGA 开发板实现简单的序列检测器-Basys2 FPGA development board to achieve a simple sequence detector
sequence_detector
- 序列检测器的设计师用Verilog语言实现的,实现了状态之间的有效处理,在FPGA开发板上可运行-module xulie_check(clk,rst,x,y) output y input clk,rst,x reg y reg [2:0] state parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7 always@(posedge clk or negedge rst)
serial1
- 基于VHDL语言实现的序列检测器,包含按键防抖动功能的实现。-Sequence detector based on the VHDL language, containing the button shake function to achieve.
The-VHDL-various-basic-code
- VHDL的各种基本代码 包括4选1,8选1多路选择器,8位全加器,加1减1计数器,序列检测器,异步清零16位加减可控计数器,数码管扫描程序,双2选1,状态机等基本程序!-VHDL basic code including 4 election 1,8 to 1 multiplexer selector, 8-bit full adder, plus 1 minus 1 counter sequence detector, asynchronous clear 16 plus or minus
xuliejianceqi
- 在FPGA开发板上用硬件描述语言实现一个状态序列检测器,比如边沿检测器等-FPGA verilog
11
- VHDL序列检测器,使用了EDA课程里面用到的状态机.-VHDL sequence detector, the use of EDA curriculum used inside the state machine.
SCHK
- ise13.2环境下VHDL编写的8位序列检测器+仿真波形-ise13.2 environment in VHDL 8 sequence detector+ simulation waveforms
seqdet_5
- 本程序是5位序列检测器的Verilog源代码,已经过上机运行检测。-This program is five sequence detector Verilog source code, has been detected on the machine running.