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detector-(1110010)
- 序列检测器(1110010)设计 ,Quartus 10.0+modelsim 6.5SE联仿真报告形式-Sequence Detector (1110010) designs, simulation with Quartus 10.0+ modelsim 6.5SE , reports
xuliejianceqi
- 序列检测器00101,包括源代码,testbench,ise13.4测试以及综合通过等说明文档。-Sequence detector 00101, the state machine verilog, testbench, ise13.4 simulation map. The test is successful
VHDL
- 先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。-First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is dete
The-state-machine
- 状态机实现序列检测器的设计,并对其进行仿真和硬件测试-The state machine implementation, the design of sequential detector and carries on the simulation and hardware test
xuliejiancejisuanqikongzhiqi
- VHDL序列检测器,计算器,控制器编码以及实现方法。-VHDL sequential detector, calculator, controller and its implementation method.
code
- 本源码是基于VHDL语言环境下的基础实验源码,共分七个部分。分别是:序列检测器、数字密码锁、四位有符号数除法、同步FIFO、DPLL的设计以及Cordic 算法实现。对于VHDL的初学者具有极大的参考价值。-The source is based on experimental basis source VHDL language environment, it is divided into seven sections. They are: the sequence detector, di
FSM
- 序列检测器,采用有限状态机实现,检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011
FSM
- 序列检测器,采用移位寄存器实现,检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
77
- 基础实验_12_有限状态机 :Moore型序列检测器-Basic experiment _12_ finite state machine: Moore type sequence detector
fsm
- verilog语言,有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
bits
- verilog语言,移位寄存器实现的序列检测器-verilog language, to achieve the shift register sequence detector
Sequence-Detector
- 利用状态机设计一个序列检测器,用以检测“1101”。用btn[1]和btn[0]作为输入分别代表1和0,输入的当前数字显示在数码管最后一位,每当新输入一个数字,之前输入的数字左移一位,依次显示出最近输入的四位数字,无输入时数码管不显示任何数字。clk时钟需要分频后才可作为检测时钟(建议分频至190Hz),每当检测到序列中有“1101”出现时,led[0]点亮,即数码显示管上显示“1101”时led[0]点亮;当按下btn[2]时恢复初始状态。-The use of a state machine
Sequence-Detector
- 序列检测器,开写为两个always语句,即为两段式有限状态机。将组合部分中的判断状态转移条件和产生输入再分开写,则为三段式有限状态机。 二段式在组合逻辑特别复杂时适用,但要注意需在后面加一个触发器以消除组合逻辑对输出产生的毛刺 。三段式描述方法虽然代码结构复杂了一些,但是换来的优势是:使FSM做到了同步寄存器输出,消除了组合逻辑输出的不稳定与毛刺的隐患,而且更利于时序路径分组,一般来说在FPGA/CPLD等可编程逻辑器件上的综合与布局布线效果更佳。-Sequence Detector
s5
- 清华大学电子系 时序逻辑实验报告 包括:触发器设计,计数器设计,累加器设计,序列检测器设计/有限状态机实现-Tsinghua University, Department of Electronics, sequential logic test report include: trigger design, counter design, accumulator design, the sequence detector design/finite state machine
VHDL-Code-and-TestBench-Code
- 实现了三个功能电路的程序:时钟分频电路;移位寄存器;序列检测器。-Including three parts:frequency divider shifting register sequential detector
seqdet
- 基于verilog hdl的10010序列检测器。-10010 sequence detector based on Verilog hdl.
sequential detector
- verilog 固定序列检测器,能够检测10111序列,波形无误。适合Verilog初学者学习(Verilog fixed sequence detector)
DDSRF-PLL
- 本文论述了在控制的一个重要方面电网连接的电源转换器,即检测基波正序分量的电网电压不平衡和扭曲的条件下。明确地,提出了一种积极的基于一种新的序列检测器双同步坐标系的解耦锁相环(双dq–PLL),完全消除了检测误差传统的同步参考框架(SRF–锁相环PLL)。(This paper deals with an important aspect in the control of grid connected power converters, that is, detecting the fundam
kebenchengxu
- VHDL代码,一些课本的小程序。包含3线-8线译码器,4选1选择器,6层电梯,8线-3线编码器,8线-3线优先编码器,8选1,BCD-7段显示译码器真值表,半加器,摩尔状态机,数字频率计,数字时钟,同步计数器,序列检测器的设计,序列信号发生器,一般状态机等等。(The small program of some textbooks. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3
1
- VHDL代码,一些课本的小程序。包含3线-8线译码器,4选1选择器,6层电梯,8线-3线编码器,8线-3线优先编码器,8选1,BCD-7段显示译码器真值表,半加器,摩尔状态机,数字频率计,数字时钟,序列检测器的设计,一般状态机等等。(VHDL code, some textbooks for small programs. Includes 3 -8 decoder, 4 1 selector, 6 elevator, line 8 Line 8 line -3 encoder, -3 prio