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daima.用VHDL语言设计一个数字秒表
- 用VHDL语言设计一个数字秒表: 1、 秒表的计时范围是0秒~59分59.99秒,显示的最长时间为59分59秒。 2、 计时精度为10MS。 3、 复位开关可以随时使用,按下一次复位开关,计时器清零。 4、 具有开始/停止功能,按一下开关,计时器开始计时,再按一下,停止计时。系统设计分为几大部分,包括控制模块、时基分频模块、计时模块和显示模块等。其中,计时模块有分为六进制和十进制计时器。计时是对标准时钟脉冲计数。计数器由四个十进制计数器和两个六进制计数器构成,其中毫秒位、十毫秒位、秒位和
2011年电子设计大赛e题《简易数字信号传输分析仪》
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码,实现后端采样同步时钟-E Electronic Design Contest 2011 problem " simple digital signal transmission analyzer" verilog source code sample to achieve the back-end clock synchronization
DigitalClock.rar
- 一个很好的数字时钟显示的例子,显示时间均为图片,A good example of the digital clock display
c822.rar
- 关于FPGA的一个设计,用FPGA来实现数字示波器,采样时钟为250M,On a FPGA design, FPGA to realize digital oscilloscope, the sampling clock for the 250M
Digital_Clock
- 单片机控制的数字时钟,能够实现分秒时的设定,显示等等。-Microprocessor controlled digital clock, minutes and seconds can be achieved when the settings, display and so on
AnClock.rar
- MFC模拟时钟控件 读取系统时间并显示 带有模拟表盘及数字时钟 当然这只是控件 需要对话框添加此控件才能起作用,MFC read analog control system time clock and display with analog and digital clock dial of course this is only the need for dialog box controls in order to add this control work
MorphDisplay
- LEDLCD数字时钟显示控件L EDLCD数字时钟显示控件LEDLCD数字时钟显示控件-LEDLCD digital clock display control LEDLCD Digital Clock Digital Clock Display Control Display Control LEDLCD LEDLCD digital clock display controls
verilogshuzishizhong
- 数字时钟的实验,让读者了解数字时钟的原理,用vhdl实现它的方法,并学习vhdl的使用技巧-Digital clock experiments, so that readers understand the principles of digital clock using vhdl way to achieve it, and learn skills to use vhdl
dsp
- 单片机的数字时钟程序,完成电脑数字时钟的自动读取-Microcontroller digital clock program, complete the computer automatically read digital clock
vhdlclock
- EDA设计实验,用VHDL编写的数字时钟代码,能显示分,秒,小时。根据所设置的频率不同,能够调整时间快慢。-EDA design of experiments, prepared by VHDL code digital clock showing the hours, seconds, hours. According to the frequency of different settings, time to adjust speed.
ClockAndCalendar
- 本系统是基于STC89C52单片机的数字时钟,实现了电子时钟和定时闹钟的的功能-The system is based on the STC89C52 single-chip digital clock, the realization of the electronic clock and timing alarm clock function
CClockST_demo
- Visual C++实现绘制数字时钟,按钮贴图。背景贴图。-Visual C++ to achieve rendering digital clock, the button mapping. Background map.
clock
- 用verilog语言实现数字时钟,有注释,规范-Digital clock using verilog language, there are notes, specifications
digitalclock
- Verilog数字时钟 实现24小时的监控,用七段码显示出来,包含时序图等 在ISE下仿真-digital clock Verilog
clock
- 用AT89C51做的数字时钟,程序很详细,还附有PROTEL图和实验报告,很好的一个东西,希望能对你有用。-This is a very very good word for your studying.
shuziluoji
- 数字逻辑课程设计,基于EWB软件设计一个数字电子时钟,要求能实现十二进制和二十四禁止的转换,有秒时分的显示,用74160实现的-Digital logic design, EWB-based software to design a digital electronic clock, the requirements to achieve 10 and 24 the prohibition of binary conversion, the second night of the show, w
desk_clock
- 可悬浮的桌面数字时钟,挺好玩儿的,可以改变大小,颜色,显示方式。-Desktop digital clock can be suspended
shuzishizhong
- 此代码是FPGA的数字时钟代码,使用的是verilog语言。-This code is the FPGA' s digital clock code, the use of the verilog language.
deskclock
- 一个桌面电子时钟。支持数字时钟日期,支持背景设置。-A desktop electronic clock. Support the digital clock date, support for background settings.
time
- 数字时钟程序,可以用vs2008编译,此程序比较简单-~