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timeconstraint
- VHDL编程中的时序约束问题，有两个PDF文件，讲的很详细，需要的立刻下载-VHDL programming timing constraints, there are two PDF documents, said very detailed, immediately download the
PPT_timing-constraint
- PPT的形式演示Xilinx-ISE环境下时序约束的实现个结果
Timing_Closure
- 一份FPGA布局布线的时序约束资料，中文描述-A FPGA placement and routing information on the timing constraints, the Chinese describe the
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
TimingConstraint
- xilinx公司提供的关于FPGA硬件设计的额时序约束参考资料-xilinx provided on the FPGA hardware design timing constraints of the amount of reference material
xilinx_timing_constains_training
- 很详细的讲解了关于xilinx时序约束的很多问题。-describe timing constains in xilinx FPGA design
FPGA_constraints
- 这是关于FPGA时序约束的文档，属于入门级介绍。在逻辑设计尤其是高速设计时，时序约束是必不可少的！-This is the documentation on the FPGA timing constraints, are entry-level introduction. High-speed logic design, especially in the design, timing constraints is essential!
top_PR
- 用户将使用具有局部重配置能力的ISE 12.1，进行综合HDL模块并完成设计。之后，使用PlanAhead12.1来布局规划设计，并内部调用执行和分析工具，包括：调用FPGA Editor查看设计实现 调用Constraint Editor创建时序约束；用Timing Analyzer进行时序分析。最后，用户可以用XUPV5开发板来进行硬件验证，并用iMPACT软件来下载全局和局部比特流。-Top-level design dynamically reconfigurable, static l
Xilinx-fpga
- xilinx时序约束的重要官方资料。非常有用-Xilinx timing constraints of important official material.
Quartus-II_TimeQuest_Constraints
- Quartus II_TimeQuest的时序约束教程，详细讲解了Quartus II工具对FPGA的时序约束。-The Quartus II_TimeQuest the timing constraints tutorial explain in detail the tools of the Quartus II FPGA timing constraints
xilinx-timing-constrains
- ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助-In this file , global timing constraints is introduced very clearly. It can really helps
Xilinx-constraints-guide2
- xilinx时序约束指南，详细的说明和使用操作实例-xilinx timing constraints
FPGA-Train
- FPGA基础培训，包括： FPGA基本架构 Xilinx工具流程 实验1：Xilinx工具流程演示 实验2：架构向导和PACE 实验3：全局时序约束 实验4：合成技术 实验5：CORE Generator系统 实验6：利用ChipScope-PRO-Basic FPGA Architecture Xilinx Tool Flow Lab 1: Xilinx Tool Flow Demo Architecture Wizard and PACE L
ddrsdram
- 一个ddrsdram时序约束文件的例子，对于fpga新手来说，是个不错的参考学习的资料-Example of of a ddrsdram timing constraints file, for fpga novice, is a good reference for learning the information
Altera-FPGA-TimeQuest
- 在Altera的FPGA中实现高速Link口的时序约束方法-The timing constraints Methods in Altera' s FPGA to achieve high-speed Link port
isen
- 基于FPGA设计工具Xilinx ISE 编写的程序代码 包含有计数器，状态转移码，交通灯，时序约束等程序-Program code written based on FPGA design tools Xilinx ISE includes procedures such as counters, state transition code, traffic lights, timing constraints
Xilinx-Timing
- Xilinx FPGA 时序约束资料，原厂出品，经典不需要理由-Xilinx FPGA timing constraint information, original, classic no reason
static-timing-analyze
- 特权同学主讲的FPGA设计的时序约束专题（STA部分）-Speaker privileged classmates timing constraints for FPGA design topics (STA section)
Xilinx-design-timing-constraints
- 很有用的Xilinx时序约束设计资料，很适合初学者-Very useful Xilinx timing constraints, design data, is very suitable for beginners
wtut_ver.ZIP
- 码表程序，完整的verilog工程文件，完整的工程设计流程，包含时序约束，ip核的嵌入，以及DCM模块的使用-Stopwatch program, complete verilog project file, complete engineering design process, including the timing constraints, ip nuclear embedding, as well as the use of DCM module