搜索资源列表
VHDL.rar
- 正弦信号发生器具有频率调节功能。采用VHDL编程实现。,Sinusoidal signal generator with a frequency adjustment function. Using VHDL programming.
DAC.rar
- 信号发生器 控制DAC输出最高100M方波、三角波、正弦波,function generator
ddfs.rar
- 基本FPGA的DDS信号发生器,可产生1-1MHZ任意频率的三角波,方波,锯齿波,正弦波,Basic FPGA-DDS signal generator, can produce 1-1MHZ arbitrary frequency triangle wave, square wave, sawtooth, sine wave
sine-generator
- 原创:采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成,可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
sin125
- 用FPGA实现DDS的信号发生器(正弦波125kHz)-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
FPGA_signal_general
- 摘 要:介绍了直接数字频率合成 (DDS) 技术的基本原理,给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案,同时给出了其软件程序和仿真结果。仿真结果表明:该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点,且输出频率可调。 关键词:直接数字频率合成;现场可编程门阵列;FPGA;三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are giv
jiyuVHDLyuyandehanshuxinghaofashengqi
- 好用的函数信号发生器,能产生多种波形,例如,正弦波,方波,锯齿波,阶梯波。-Useful function signal generator, can produce a variety of waveforms, for example, sine wave, square wave, sawtooth, wave ladder.
signal_generator
- 基于vhdl的多功能函数信号发生器的设计,能实现三角波、方波、正弦波。-VHDL-based multi-function signal generator design, can achieve the triangular wave, square wave, sine wave.
sin
- 正弦信号发生器源文件实现正弦信号发生器,非常有用,欢迎下载。-Sinusoidal signal generator source file achieve sinusoidal signal generator, very useful and welcome to download.
example10
- :正弦波发生器例程,包括了直接数字频率合成(DDS)的原理以及如何应用CPLD产生频率可控频率的正弦信号。-: Sine wave generator routine, including a direct digital synthesizer (DDS), as well as the application of the principle of frequency control CPLD generated sinusoidal signal frequency.
EP1C3_12_10_PHAS
- 基于FPGA的移相式DDS正弦信号发生器的VHDL源代码,压缩包里是在Quartus里做的工程,FPGA用的是Cyclone1C3系列-FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series
signal
- verilog写的串口控制信号发生器,能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
Sine
- 标准正弦信号发生器,并且含有正弦表,对于新手有些帮助-Standard sinusoidal signal generator, and contain sinusoidal form, and some help for novice
DDS
- dds 正弦信号发生器步进100HZ 最高频率可达900kHZ 最低频率可大2.3Khz-dds signal generator sin walingbeam 100HZ
FPGA_VHDL_sinusoidal_function
- 该文件包含基于VHDL的正弦信号发生器的设计源码-This file contains the VHDL-based design of sinusoidal signal generator source code
DDS
- 采用DDS实现数字信号发生器, 时钟频率为100MHz,可输出1K到10M的正弦波-use Direct Digital Synthesizer realize SINA wave
zhenxianxinhao
- 此文件是正弦信号发生器实验的源码,这是老师的资料,对课堂很有帮助-This file is the sine signal generator with source code, it is the teacher of information helpful to the classroom
dds信号发生器
- dds正弦信号发生器源代码,适合处于学VHDL学生查阅