搜索资源列表
bcd
- EDA 十进制计数器、BCD VHDL源代码-EDA decimal counter VHDL source code
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
liushi
- 模60、5计数器 实现计数功能，以00-59或00-04循环-60.5 Counter modulus function to achieve count to 00-59 or 00-04 cycle
Untitled
- 59秒计数器实验程序，适用于PIC18F4520单片机，从0—59计数-Experimental procedures for 59 seconds counter for PIC18F4520 microcontroller, counting from 0-59
22
- 使用VHDL实现16进制的计数器的算法程序-Use VHDL to achieve 16 of the counter-band algorithm procedure
MCU00to99counter
- //00-99按键计数器每按一次加一显示 //软件延时 //已经测试-//00-99 key counter increases every time a show// software delay// have been tested
DAQCounter
- 利用DAQCounter控件实现板卡计数器输入-The realization of the use of control boards DAQCounter counter input
bcd99
- 设计了一个计数范围是0到99的BCD计数器并可以显示出来的-Designed a range of counts 0-99, and the BCD counters can be displayed
1602
- 基于单片机的stc89c52rc的实验 1602液晶显示与计数器倒计时计数-Based on the experimental SCM stc89c52rc liquid crystal display with 1602 count countdown counter
counter
- 这是用VHDL设计的十进制计数器，两个VHDL程序分别说明了out和buffer的区别-It is designed with VHDL decimal counter, the two VHDL procedures were illustrated the difference between out and buffer
newjs
- 0-999计数器，通过定时器中断扫描，可以实现0到999之间的计数工作。-0-999 counter, scanning through the timer interrupt, can be between 0-999 count work.
Detailed
- ASP计数器设计详解 -Detailed design of ASP counters
8253timer
- 一个关于8253可编程定时器计数器的源代码....还有仿真-8253 programmable timer on the counter there are simulation source code .... .....
65536
- （1） 计数器的输入为RST（复位），EN（使能），CLK（时钟），U_D（up_down加/减选择）；输出为COUT（进位/借位输出），CQ（3：1）（数值输出）； 范围65536。 -failed to translate
web
- 动态数据库网站，含有主页，BBS，论坛，购物系统，计数器等。-Dynamic database website, which contains Home, BBS, forums, shopping systems, counters, etc..
1_frequency_counter
- BJ-EPM240V2实验例程以及说明文档实验之一 分频计数器-BJ-EPM240V2 experimental routine, as well as documentation of the experimental frequency counter
Johnson_Counter
- BJ-EPM240V2实验例程以及说明文档实验之三Johnson 计数器-BJ-EPM240V2 experimental test routines as well as documentation of the three Johnson Counter
times
- 计数器，用VHDL实现，先6分频，再10分频，24分频，同时可做万年历-Counter, using VHDL realization frequency first 6 hours, 10 minutes and then the frequency, frequency of 24 minutes, at the same time to do calendar
Led
- 本程序有效的防止了按键的抖动，可以移植于各种需要按键防抖的程序，本程序是功能为按键防抖16进制减法计数器-debounced counter VHDL
DIP_PB_Counter
- 本程序有效的防止了按键的抖动，可以移植于各种需要按键防抖的程序，本程序是功能为按键防抖16进制减法计数器-This procedure prevents the effective jitter keys can be transplanted into a variety of procedures need to Anti-Shake button, the program is anti-shake function for the key 16 counter-band subtract