搜索资源列表
watch
- 一个用VHDL编程基于CPLD的EDA实验板开发可以实现顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S,用三位数码管显示。 (1) 倒计时:通过小键盘可以实现设定计时时间(以秒为单位,最大计时时间为99.9秒)。通过键盘实现计时开始、计时结束。当所设定的倒计时间到达00.0S后,自动停止倒计时,同时响铃。 (2) 顺计时:初始值为00.0S,通过键盘实现开始计时和结束计时功能。计时结束后,显示记录的时间。 (3) 用三个发光二极管正确显示以下状态:倒计时状态、顺计时状态
VHDL_code_for_DAC_controller
- 一个VHDL代码设计时,它是控制 在AD7524数字至模拟转换器-An VHDL code designs are presented ,it is for controlling the AD7524 digital-to-analogue converter
VHDL1
- 四路抢答器。自锁,灭灯,响闹,计时,显示。-Four ways of vies to implement VHDL source language
30daojishi
- 30秒倒计时器,基于VHDL语言。具有循环计时功能,-30 seconds countdown timer, based on the VHDL language. With a cycle time function,
Marquee
- VHDL语言设计的跑马灯程序,使用8段数码管,并能递减计时,计时时间到蜂鸣器响声输出,数据在数码管上滚动显示,在试验箱上测试通过。-Marquee VHDL language design process, with 8 of the digital control, and can decrease time, time time to sound the buzzer output, data on the digital scroll in the chamber on the test.
cntm60
- VHDL实现的60s计时器,用于时钟控制电路,实现计时。-the 60 seconds timer based on VHDL is used to controling the electronic circuit of timer.
wtut_vhd
- spartan 3E 1600开发板的秒表计时器源程序,VHDL语言-source code of timer on spartan 3E1600 development board in VHDL
a_vhdl_8253_timer_latest[1].tar
- 因特尔8254 计时器的vhdl语言实现-a VHDL version of the Intel 8254 timer
VVHDL_32bit_tH
- VHDL写的32位计数,两个四位共阳数码管输出串口输出+数码码管显示的计时器程序每次停止后串口输出。,已通过测试。 -VHDL written 32 count, two four sun digital serial output tube output serial output the+ digital code to display the timer program each stop. , Has been tested.
div50m
- 用VHDL代码编写的50分频器,已经经过Quarter仿真,证明正确,可用于计时器中-50 divider using VHDL code has After Quarter simulation, proved correct, can be used in the timer
clock
- 数字计时器的vhdl实现,quartus 和 modelsim 仿真-Digital timer vhdl achieve quartus and modelsim simulation
eclock
- 使用vhdl语言实现一个集计时器,闹钟,整点报时为一体的电子钟-Electronic clock VHDL language as one of a set timer, alarm clock, the whole point timekeeping
minute_ct
- 采用VHDL语言设计的分钟计时器,是时钟设计的一部分,已仿真和测试通过。-Design using VHDL-minute timer, the clock part of the design, simulation and testing has been passed.
VHDL
- (1)抢答器可容纳四组选手,并为每组选手设置一个按钮供抢答者使用; 为主持人设置一个控制按钮,用来控制系统清零(组别显示数码管灭灯)和抢答开始。 (2)电路具有对第一抢答信号的锁存、鉴别和显示等功能。在主持人将系统复位并发出抢答指令后,提示抢答开始,计时显示器显示初始时间并开始倒计时,若参赛选手按下抢答按钮,则该组别的信号立即被锁存,并在组别显示器上显示该组别,同时扬声器也给出音响提示,此时,电路具备自锁功能,使其他抢答按钮不起作用。 (3)主持人对抢答结果进行确认,给出倒计时计数允许信
timer
- 基于VHDL语言的一个简单秒表,包含按键消抖模块、数码管译码、计时器等模块。直接适用于basys2和nexys3两个开发板。更改ucf文件后适用于其他开发板-A simple stopwatch based on VHDL, including key debounce module, digital decoder, timers and other modules. Directly applicable to basys2 and nexys3 two development boards
time
- 年月日时分秒计时器,基于VHDL的表,爱爱爱啊-YYMMDDHHMMSS timer
time
- 利用quatars,vhdl实现有倒计时功能计时器,设计定时器功能有正向计时和倒向计时,可暂停计数,继续计数。当倒向计时计数为0时会报警(时间为1分钟)在报警期间可以认为关闭-Using quataus, VHDL realization which has the function of the countdown counter, timer design features are timing and backward timing, can suspend count, continue
VHDLstopwatch
- 采用vhdl硬件描述语言实现的秒表计时器程序源码及顶层电路设计图,实现了计时器,数码管显示,按键控制及蜂鸣器等功能-Using VHDL hardware descr iption language to realize the stopwatch timer program source code and top-level circuit design, the timer, digital tube display, control buttons and a buzzer functio
shuzijishiqi
- 基于VHDL的数字计时器,手动可控正计时和倒计时(含复位键和使能键)-VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key)
60s qiangdaqi
- 1.抢答器同时供N名选手,(此处假设4个)分别用4个按钮S0~?S3表示。? 2.设置一个系统“开始复位”开关S,该开关由主持人控制(当主持人按下该开关后以前的状态复位并且开始计时抢答)。?3.抢答器具有锁存与显示功能。即选手按动按钮,锁存相应的编号,并在LED数码管上显示,同时扬声器发出报警声响提示。选手抢答实行优先锁存,优先抢答选手的编号一直保持到主持人将系统清除为止。?(1. Responder at the same time for N players, (here assumed