搜索资源列表
BitHound_SP601_1.0_
- 逻辑分析仪器代码，VHDL实现，支持100M采样速度-Logic analysis instrumentation code, VHDL implementation, support 100M sampling rate
sin
- 这是一个基于vhdl编写的正弦信号发生器，实现的功能为发生正弦波，给dac 0832采样-This is a sine signal generator based on VHDL code, realize the function of sine wave, give dac 0832 samples
ADVHDL
- 用fpga控制ad采集，用vhdl编写，可控制采样率-With fpga control ad acquisition, with vhdl written to control the sampling rate
upsampler
- 一个用VHDL自行编写的完整可行的增采样系统，仅供参考-VHDL with a self-preparation of a complete and feasible by sampling system, for reference only
myAdc9248
- CycloneIV控制采样芯片AD9248-20MHz，VHDL语言-CycloneIV control sampling chip AD9248-20MHz, VHDL language
cordic
- 改进的cordic算法的vhdl程序,采样资源换时间的办法用最少的旋转级数获得最大的计算精度-mvr-cordic algorithm vhdl program
epm240_example
- VHDL代码，共10个程序，分别是1分频器2状态机3计数器4拨码开关对应数码管显示5键盘及显示6键盘显示7交通灯8汉字滚动9ADC0804直流采样和显示10正弦波发生器(A total of 10 procedures, namely, 1 frequency dividers, 2 state machines, 3 counters, 4 dial switches, corresponding to digital tube display 5 keyboard and display 6
FSK调制的FPGA实现
- 使用DDS核实现cpfsk的VHDL设计，采样频率fs为32Rb