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Single-CPU-clock-cycle-
- 单时钟周期CPU的设计实验，能完成16条基本指令。-Single CPU clock cycle of experimental design，Article 16 to complete basic instructions。
PipelineCPU
- 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt
CPU-project
- 硬件实验 设计一个给定指令系统的处理器 支持多条指令带进位和不带进位的ADD，SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,清零等等，内有设计报告-Hardware experiment，design a CPU with the command following:SUB，OR, AND, MOV, MVI, STA, LDA, JZ, JMP,clear, and so on.There is a disigning report in it.
CPU-with-VHDL-16-32
- 在quartus中运行的32位指令集的16位CPU程序，模块化设计，包括MBR, BR, MR, ACC, MAR, PC, IR, CU, ROM, RAM, ALU等模块-In the the quartus run 32 16-bit CPU instruction set procedures, modular design, including the MBR, BR, MR, the ACC, the MAR, the PC, the IR CU, the ROM, RAM, ALU
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
lab05_09122011
- 多周期CPU设计，可以实现22条基本指令。实现简单，包含实验报告-CPU design
lab06
- 流水线CPU设计，最接近真实运行的学生实验课的CPU设计，是组成原理实验课大作业，包涵详细讲解-CPU design
8_RISC_CPU
- risc-cpu，简单的cpu设计,强大的功能简洁的设计，精简化-verilog risc_cpu
yuanma
- MIPS指令源代码，用于CPU设计，计算机组成原理课设所需要的源代码下载-MIPS instruction source code for the CPU design, computer composition principle lesson to set the source code download
16-bit-CPU
- 单周期16位CPU的设计,我们的计算机组成原理课设，可以实现R型、I型和J型指令，内有报告和指导书-Single-cycle 16-bit CPU design, our Principles of Computer Organization class set, you can achieve R-type, type I, and J-type instructions, reports and instructions
TVerriRiscCPPh
- 这个文件中使用verilog hdl简单易懂懂的运用基本运算实现了微型的cpu设计开发过程 -Verilog hdl straightforward to understand the use of basic operations miniature cpu design and development process used in this document
cpu
- cpu的设计，能实现转移指令，数据算数运算，逻辑运算，移位，中断等功能-It s about the design of CPU
zreda7
- 详细具体的cpu设计maxplus源代码（附图）能完成cpu的基本功能。-Cpu design maxplus detailed and specific source code (with photos) to complete the basic functions of cpu.
VHDL-cpu
- 根据计算机组成原理课程所学的知识和本课程所讲的设计思想，设计一个给定指令系统的处理器，包括：VHDL语言的实现；FPFA芯片的编程实现； -Based on the knowledge and the curriculum computer architecture course learn about design thinking, design a given the instruction system' s processor, including: the realizat
MiniCPU
- 16位 迷你CPU 设计， 包含 20条指令和TEST BENCH-16 mini CPU design.
RISC_CPU
- 一个32位流水线 CPU 设计， 含设计文档和模拟图。-A 32-bit pipelined CPU design, including design documentation and simulation in Fig.
cpu
- 《vhdl编程实例》（第四版）内的cup设计源代码 -Cup design source code " vhdl programming examples" (fourth edition)
mips-cpu
- 一个组成原理的课程设计，完成一个流水线MIPS CPU的设计，有详细的说明及其代码，实测可用-a project about the design of MIPS CPU
logism
- logism cpu设计，单周期16位cpu，实现了几种指令包括R &ri& i-logism design CPU
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.