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pro_2
- 简单CPU设计。使用Verilog语言，比较简单易懂。-simple CPU
TCAM_2
- 经典RISC CPU 设计，和PCI8位指令单片机兼容，值得初学者看一下-Classic RISC CPU design, and PCI8 bit microcontroller compatible instruction, it is worth a look for beginners
CPU
- 设计一段程序来模拟优先级调度算法和时间片轮转算法。可以指定进程的数量、各进程需要CPU的时间和各进程的优先级。-Design a program to simulate the priority scheduling algorithm and the time slice rotation algorithm. You can specify the process of quantity, the process requires CPU time and the process prior
CPU
- 组成原理课设，简单CPU微处理器指令系统设计。-CPU design
EDAandVHDL3
- 包含本系列的第三部分内容，详细介绍了VHDL状态机的概念及其使用和16位CISC CPU设计。-The third part contains the contents of this series, detailing the concept and its use of 16-bit CISC CPU design and VHDL state machine.
OpenMIPS_VerilogHDL_Study_v1.1
- 10天用verilog实现MIPS_cpu，内有清晰结构图。很好的cpu设计学习资料！-10 days with verilog achieve MIPS_cpu, within a clear structure diagram. Good cpu design learning materials!
Nios_II-CPU
- nios 处理器嵌入式系统设计，介绍了nios ii处理器的基本特点以及构建一个最小的嵌入式系统hello_world-NIOS CPU embedded system
cpu
- 设计一个CPU,微程序控制器部件实验,包括部件的源码打开可运行 -The design of a CPU, micro program controller component test, including parts of the source code open operation
Our_MIPS_CPU
- 基于MIPS架构的CPU设计，含有完整程序代码，及各模块实现及仿真程序！-CPU design based on MIPS architecture, contains a complete code, and the realization of each module and the simulation program
code
- Mips单周期CPU设计（支持7条指令addu、subu、ori、lw、sw、beq、lui）-Mips single-cycle CPU design
CPU
- 运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。-Using vhdl hardware descr iption language developm
simple_CPU_VHDL
- 简单的CPU的VHDL设计 vhdl代码和cpu设计过程--Simple CPU design of the VHDL code and VHDL design process cpu
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
RISC_CPU1
- 讲述了简易cpu设计的全部过程，代码详细，对于一个初学者是很好的范本-About the whole process, the simple design of CPU code, for beginners is a very good model]
CPU1
- 一个简单的多周期的基于MIPS的CPU设计-cpu VHDL
RISC_CPU
- RISC cpu设计，verilog语言，PIC14位指令集-RISC cpu design, verilog language, PIC14-bit instruction set
CPU
- 使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。-Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.
simple_cpu
- 一个简单的cpu设计，用verolog hdl语言设计的，希望对你们有用-simple cpu design
8BIT_CPU
- 一个8位的CPU设计，用verilog语言写的，希望有用-A CPU OF 8 BITS
CPU
- 设计一个简易cpu，包含指令集，能够实现有限指令的操作，具体见内部文档-Design a simplified CPU that has its own instructions which it can work with.