搜索资源列表
CycloneII_2C35
- 基于cyclone II 的视频解码程序,-Cyclone II-based video decoding process,
hex2rom_0241_Win32
- This SPI-mode SD Card controller is a free SOPC Builder component that can be used in any SOPC Builder system. The included example design runs on the Nios II Embedded Evaluation Kit, Cyclone III edition (NEEK).-This SPI-mode SD Card controller is a
CycloneEP2C20
- 自己辛苦了1个月设计的FPJA试验板，求大家验证一下，主要是用Cyclone II EP2C20 设计的-Their hard work on the design of a test board FPJA seeking people to test, primarily designed to use Cyclone II EP2C20
Bufor
- Circular buffer using a cyclone memory ( Quartus II and VHDL .)-Circular buffer using a cyclone memory ( Quartus II and VHDL .)
LAB_ATTEMPT2
- Verilog and SOPC implementation of interrupts for DE2 board and Cyclone -Verilog and SOPC implementation of interrupts for DE2 board and Cyclone II
YYPP
- 计算机组织与系统结构实验 用一个74182芯片和四个74181芯片构成一个4位逻辑算数运算器，实现平台为Cyclone II EP2C35F672C6-Computer Organization and Architecture Designing for Performance Experiment
exercicio4
- VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone -VHDL program. Calculator that do basic operations. Add, subtract, divide and multiplication using Cyclone II
HexatoSSD
- VHDL program. It s a converter from Hex to SSD format using Cyclone -VHDL program. It s a converter from Hex to SSD format using Cyclone II
TrafficLightController
- It s a vhdl program. Simulates a traffic light controllet using a Cyclone II FPGA
UserDefinedFunction
- It s a VHDL program. The program does a generic gray. Using a Cyclone II FPGA Board.
irDA
- irDA的VHDL程序及开发资料,在cyclone II上完美编译-irDA of VHDL procedures and development of information compiled in cyclone II on the perfect
Cyclone_II_FPGA_Minimum_System
- Cyclone II FPGA最小系统电路连接方式。包含JETAG配置和PLL配置-Minimum System Cyclone II FPGA circuit connections. Configuration and PLL configuration contains JETAG
Shiftregister
- A simple realisation code of a shift register written on VHDL in Quartus II for Cyclone II. The programm can store or shift the input data to left or right depending on which mode is chosen.Can be useful for the students.
CLOCK-ON-ALTERA-DEV-NOARD-RONTEX
- 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试. 文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等. 调试步骤就不讲了,管脚分配请网友自行完成. 开发板 Altera Cyclone II EP2C35F672C6 软件平台 Quartus II 语言 verilogHDL-These are all the project
PaintBrush
- To use the device port ISP1362 and NIOS II CPU for mouse movement detection and the VGA interface and implement a Paint Brush Application[1] using Cyclone II FPGA on the Altera DE2 board.
FPGA
- 本文采用FPGA来模拟实际的乒乓球游戏。本设计是基于Altera 公司的FPGA Cyclone II 芯片EP2C35 的基础上实现，运用Verilog HDL 语言编程，Quartus II 软件上进行编译、仿真，最终在Altera 公司的DE2 开发板上成功实现下载和调试-In this paper, FPGA to simulate the actual tennis game. The design is based on Altera' s FPGA Cyclone II EP
EP2C8Q_Nios_LED
- CYCLONE II NOIS例程,学习NIOS入门例程-CYCLONE II NOIS routines, learning NIOS entry routine
hw5
- Design a 2-digit stopwatch that ticks every second. A switch is used to start and stop the time. When the switch is pushed, the time will start and when it is pushed again, the time will stop. In order for the switch to work properly, the switch must
multifunction-digital-clock
- EDA课程设计多功能数字时钟的设计程序源码，在Cyclone II上验证成功！-EDA curriculum design process multifunction digital clock source, the Cyclone II verify success!