搜索资源列表
dds
- 基于FPGA的DDS函数信号发生器代码DDS-may cause permanent damage to the device
DDS
- dds的fpga实现,用的是VHDL语言，希望能帮到大家-dds of fpga implementation, using a VHDL language, we hope to help
DDS
- 用FPGA实现DDS数字式频率合成器（Direct Digital Synthesizer）-FPGA implementation using digital frequency synthesizer DDS (Direct Digital Synthesizer)
dds
- 基于fpga的数字移相信号发生器，本文设计的数字相移信号发生器以直接数字频率合成（DDS）技术为核心，用现场可编程门阵列（FPGA）来实现频率和相位的预置和改变，并完成信号的频率和相位差显示。设计中采用的是直接数字频率合成（DDS）技术-Fpga-based Digital Signal Generator shift, the paper design of digital phase-shift signal generator for direct digital frequency sy
dds
- DDS信号发生器 TLV5639，FPGA DDS信号发生器 TLV5639，FPGA-DDS signal generator TLV5639, FPGA DDS signal generator TLV5639, FPGA DDS signal generator TLV5639, FPGA
FPGA-DDS
- 直接数字频率合成器，产生频率可控的信号源。-Direct digital frequency synthesizer to generate controlled frequency source.
DDS
- 实现了基于FPGA的DDS信号源设计，能同时两路输出，输出波形包括正弦波、三角波、方波和锯齿波，且其频率和相位均可调，还能计算两路输出信号的相位差。-FPGA-based implementation of the DDS signal source design, two outputs simultaneously, the output waveforms including sine, triangle, square and sawtooth waves, and its freque
triangle_LFM
- DDS芯片产生三角波线性调频信号的FPGA程序-DDS chip generated triangular wave linear FM signal of the FPGA program
DDS-TEST-4
- 用FPGA实现DDS，有正弦，三角，方波，方波可调占空比，频率可调。能做到100K左右。-Using FPGA DDS, a sine, triangle, square, adjustable duty cycle square wave, frequency adjustable. Can do about 100K.
dds
- 通过查表法，用FPGA实现波形的输出。预先将数据存放在ROM中，依次读取数据并输出。-Look-up table method, the output waveform with FPGA implementation. Advance to data stored in ROM, in order to read data and output.
DDS_sine
- DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
ALTERA@FPGA@example
- 基于ALTERA的几个VHDL实例，如FPGA单片机，DDS的正弦信号发生器，FPGA视频监控-VHDL example：such as DDS Sine signal generator
FPGA_DDS
- FPGA中实现信号发生器,即DDS,代码简洁,精练,非常适合学习,已经经过验证.-The FPGA signal generator, or DDS, the code simple, concise, very suitable for learning, has been verified.
vhdl-ad9910
- ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明： Filename Function ----------------------------------------------------- dds_controller.vhd top entity, opcode decoding ddslib.vhd configuration,opcode definition dds_serial.vhd parallel to s
DDS
- 一种基于FPGA的DDS设计方案与仿真实现-FPGA-based design and simulation to achieve DDS
MY-DDS
- 利用altera公司的FPGA使用verilog语言实现DDS功能 外加DA 可将数字信号转换成标准正弦信号-Altera FPGA use verilog language of DDS functions plus DA converts digital signals into a standard sine signal
FPGA-ET
- DDS generator programe 产生-DDS generator advanced programe
DDS
- 基于FPGA的DDS信号发生器，实现简单的余弦信号输出- 基于FPGA的DDS信号发生器，实现简单的余弦信号输出
DDS
- 基于FPGA的直接数字频率合成技术的源代码-Direct digital frequency synthesis
DDS
- 基于VHDL的DDS设计代码，进过仿真验证，斌在FPGA实验板上实现-dds design