搜索资源列表
FIFO
- 基于FPGA的FIFO控制器的设计与实现,ISE,verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
FIFO64
- FIFO级联,利用verilog语言实现Xilinx FIFO18单元的多个级联,增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
FIFO_8_8
- FIFO先进先出队列,一种缓存、或一种管道、设备、接口(Verilog HDL程序,内附说明)-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
FX2_Slave_FIFO
- cy68013的从FIFO方式的通信源代码-cy68013 from the FIFO mode of communication source code
asfifodesign
- 异步fifo设计文档,里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
FIFO-verilog
- 两种异步FIFO设计以及源代码(Verilog)-Two asynchronous FIFO design and source code (Verilog)
FIFO
- 异步FIFO国外经典教程,包含两篇重量级文献 -Asynchronous FIFO foreign classic tutorials, including two heavyweight literature
OV7670
- STM32 驱动 OV7670 摄像头 FIFO
mem_ctrl_latest.tar
- 存储器控制FPGA程序,包括ram,fifo,sdram,flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
pingpang
- FIFO读写,用使用状态机完成两片FIFO读写,乒乓操作。-FIFO read and write, using the state machine complete with two FIFO read and write, ping-pong operation.
shiyan3niu
- 1.利用FLEX10KE系列(EPM10K100EQC240-1X)的CLOCKBOOST (symbol:CLKLOCK),设计一个2倍频器,再将该倍频器2分频后输出。 对其进行时序仿真。 2.设计一个数据宽度8bit,深度是16的 同步FIFO(读写用同一时钟),具有EMPTY、FULL输出标志。 要求FIFO的读写时钟频率为20MHz, 将1-16连续写入FIFO,写满后再将其读出来(读空为止)。 仿真上述逻辑的时序,将仿真
uart_fifo
- avr单片机串口先进先出实例程序,这是个人在实际项目中应用的一个例子,还有是定时器的使用方法-Examples of single-chip FIFO serial avr procedures, which are individual projects in the actual application of an example are also the use of timer
fifo
- 模拟操作系统进程调用的一个fifo先进先出的程序-Simulate the process of the operating system calls the program a fifo FIFO
fifo
- 基于verilog的异步fifo设计,仿真效果良好-asynchronous fifo based on zhe verilog language
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
Verilog
- 异步fifo的经典写法,使用verilog语言编写的。-Asynchronous fifo' s classic formulation, using verilog language.
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
program
- 设计实现4bit FIFO, 数据深度为8, 产生满, 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the fi
CY7C68013FPGA
- USB控制芯片cy7c68013与FPGA通过slave fifo方式通信,块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
DSP_2812_SCI_232
- DSP2812串口通信编程,利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code