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- 用JAVA实现操作系统的页面置换 其中包括 最佳置换算法(Optimal)、先进先出算法（First-in, First-out） 、最近最久不用的页面置换算法（LeastRecently Used Replacement）三种算法的实现-JAVA realization of the operating system with replacement pages including the best replacement algorithm (Optimal), FIFO algorit
altera_fifo
- altera 公司的 FIFO 文档，这是设计同步或异步FIFO的重要文档-altera s FIFO document
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
ADS
- ads8365的高速采集程序，采样率100kbps,6通道同步采样，采用FIFO模式-ads8365 high-speed acquisition procedures, sampling rate of 100kbps, 6-Channel Simultaneous Sampling, using FIFO mode
fifo的vhdl原代码
- 本文为verilog的源代码-In this paper, the source code for Verilog
FIFO_Design
- 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
FPGA_FIFO
- 使用Verilog编写的同步FIFO，可通过设置程序中的DEPTH设置FIFO的深度，FIFO_WRITE_CLOCK上升沿向FIFO中写入数据， FIFO_READ_CLOCK上升沿读取数据。本程序对FIFO上层操作简单实用。-Prepared by the use of Verilog synchronous FIFO, through the setup program in the FIFO depth DEPTH settings, FIFO_WRITE_CLOCK rising
cache
- （1）FIFO：First In First Out，先进先出 （2）LRU：Least Recently Used，最近最少使用 （3）LFU：Least Frequently Used，最不经常使用-（1）FIFO：First In First Out （2）LRU：Least Recently Used （3）LFU：Least Frequently Used
13
- para13： fifo.vhd FIFO（双口RAM） fifo1.vhd FIFO（嵌入式EAB） fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
CuFIFO
- fifo的vhdl代码,比较简单，适合初学。-fifo the VHDL code, is relatively simple, suitable for beginners.
FIFO
- 操作系统实践课程实验，页面置换的4种方法，FIFO等-Practice Course experimental operating system, page replacement of the four kinds of methods, FIFO, etc.
fifo
- fifo程序，供大家参考参考，给点意见，初次编写-fifo procedures for your information, to the point, the initial preparation of
fifo
- 在c环境下模拟操作系统中的先来先服务算法.-C simulation environment in the operating system of first come first serve algorithm.
FIFO1
- FIFO存储电路的设计与实现，用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
fifo
- 先入先出缓冲存储器，采用verilog hdl-FIFO buffer memory, using verilog hdl
2812SPIFIFO
- 使用spi fifo中断进行接受和cputimer中断里进行发送-Carried out using the spi fifo interrupt acceptance and interrupt cputimer conducted Send
asyn_fifo
- verilog编写的异步fifo源代码，asyn_fifo.v为顶层，调用其他四个文件-asynchronous fifo prepared Verilog source code, asyn_fifo.v for top-level, call the other four documents
ASYNCFIFOXPXMOD
- 任意时钟配比的异步fifo.含有synplify ip库中的双端口ram。用于处理多时钟域问题。-Arbitrary ratio of asynchronous clock fifo. Containing synplify ip library of dual-port ram. Used to deal with the issue of multi-clock domain.
usbin_v1.7
- 用于cy7c68013与fpga的从FIFO通讯.版本1.7-For the CY7C68013 and FPGA communications from the FIFO. Version 1.7